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V62/04736-01XE PDF预览

V62/04736-01XE

更新时间： 2024-02-03 04:55:29
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
12页 402K
描述
SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT

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V62/04736-01XE 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：TSSOP, TSSOP5/6,.08针数：5
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：6 weeks风险等级：5.22
Is Samacsys：N控制类型：ENABLE HIGH
计数方向：UNIDIRECTIONAL系列：LVC/LCX/Z
JESD-30 代码：R-PDSO-G5JESD-609代码：e4
长度：2 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.032 A
湿度敏感等级：1位数：1
功能数量：1端口数量：2
端子数量：5最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP5/6,.08
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：3.3 V最大电源电流（ICC）：0.01 mA
Prop。Delay @ Nom-Sup：4.5 ns传播延迟（tpd）：8 ns
认证状态：Not Qualified座面最大高度：1.1 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A宽度：1.25 mm
Base Number Matches：1

V62/04736-01XE 数据手册

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SCES527A − DECEMBER 2003 − REVISED MAY 2004  
D
D
Controlled Baseline  
− One Assembly/Test Site, One Fabrication  
Site  
D
D
D
D
D
Low Power Consumption, 10-µA Max I  
24-mA Output Drive at 3.3 V  
CC  
I
Supports Partial-Power-Down Mode  
off  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
Operation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
D
D
D
D
D
Enhanced Product-Change Notification  
†
Qualification Pedigree  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
Supports 5-V V  
Operation  
CC  
Inputs Accept Voltages to 5.5 V  
− 1000-V Charged-Device Model (C101)  
Max t of 3.7 ns at 3.3 V  
pd  
†
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
DCK PACKAGE  
(TOP VIEW)  
1
2
3
5
4
OE  
A
GND  
V
Y
CC  
description/ordering information  
This single bus buffer gate is designed for 1.65-V to 5.5-V V  
operation.  
CC  
The SN74LVC1G126 is a single line driver with a 3-state output. The output is disabled when the output-enable  
(OE) input is low.  
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a  
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the  
driver.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
‡
T
A
PACKAGE  
§
−40°C to 85°C  
SOT (SC-70) − DCK Reel of 3000  
CLVC1G126IDCKREP  
CN_  
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
DCK: The actual top-side marking has one additional character that designates the assembly/test site.  
§
FUNCTION TABLE  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
H
H
L
H
L
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

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