Datasheet > V58C265164S

V58C265164S

更新时间： 2022-11-27 16:17:42

品牌	Logo	应用领域
MOSEL		动态存储器双倍数据速率
页数	文件大小	规格书
44页	451K
描述
64 Mbit DDR SDRAM 2.5 VOLT 4M X 16

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V58C265164S 数据手册

V58C265164S

64 Mbit DDR SDRAM

2.5 VOLT 4M X 16

PRELIMINARY

MOSEL VITELIC

System Frequency (f

)

250 MHz

4 ns

225 MHz

4.5 ns

200 MHz

5 ns

183 MHz

5.5 ns

Clock Cycle Time (t

)

CK3

)

4.8 ns

6 ns

5.4 ns

6 ns

6.6 ns

CK2.5

)

6.75 ns

7.5 ns

8.25 ns

CK2

Features

Description

ꢀ 4 banks x 1Mbit x 16 organization

ꢀ High speed data transfer rates with system

frequency up to 250 MHz

The V58C265164S is a four bank DDR DRAM

organized as

4 banks x 1Mbit x 16. The

V58C265164S achieves high speed data transfer

rates by employing a chip architecture that

prefetches multiple bits and then synchronizes the

output data to a system clock

All of the control, address, circuits are synchro-

nized with the positive edge of an externally sup-

plied clock. I/O transactions are possible on both

edges of DQS.

ꢀ Data Mask for Write Control (DM)

ꢀ Four Banks controlled by BA0 & BA1

ꢀ Programmable CAS Latency: 2, 2.5, 3

ꢀ Programmable Wrap Sequence: Sequential

or Interleave

ꢀ Programmable Burst Length:

2, 4, 8 for Sequential Type

2, 4, 8 for Interleave Type

Operating the four memory banks in an inter-

leaved fashion allows random access operation to

occur at a higher rate than is possible with standard

DRAMs. A sequential and gapless data rate is pos-

sible depending on burst length, CAS latency and

speed grade of the device.

ꢀ Automatic and Controlled Precharge Command

ꢀ Suspend Mode and Power Down Mode

ꢀ Auto Refresh and Self Refresh

ꢀ Refresh Interval: 4096 cycles/64 ms

ꢀ Available in 66-pin 400 mil TSOP-II

ꢀ SSTL-2 Compatible I/Os

ꢀ Double Data Rate (DDR)

ꢀ Bidirectional Data Strobe (DQs) for input and

output data, active on both edges

ꢀ On-Chip DLL aligns DQ and DQs transitions with

CLK transitions

ꢀ Differential clock inputs CLK and CLK

ꢀ Power supply 2.5V 0.2V

Device Usage Chart

Operating

Temperature

Range

Package Outline

CLK Cycle Time (ns)

Power

Std.

Temperature

Mark

JEDEC 66 TSOP II

-4

-45

-5

-55

0°C to 70°C

•

Blank

V58C265164S Rev. 1.7 August 2001

12 3 4 5 6 7...44

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