Datasheet > UT6264CPCL-35

UT6264CPCL-35

更新时间： 2024-11-21 00:43:11

品牌	Logo	应用领域
其他 - ETC		静态存储器光电二极管内存集成电路
页数	文件大小	规格书
10页	208K
描述
8K X 8 BIT LOW POWER CMOS SRAM

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UT6264CPCL-35 数据手册



UTRON

UT6264C

8K X 8 BIT LOW POWER CMOS SRAM

Rev. 1.1

FEATURES

The UT6264C is a 65,536-bit low power CMOS

static random access memory organized as 8,192

words by 8 bits. It is fabricated using high

performance, high reliability CMOS technology.

Access time : 35/70ns (max.)

ꢀ

Low power consumption :

ꢀ

Operating : 45/30 mA (typ.)

CMOS Standby : 2mA (typ.) normal

2 µA (typ.) L-version

Easy memory expansion is provided by using two

chip enable input.(

,CE2) ,and supports low

CE1

1 µA (typ.) LL-version

data retention voltage for battery back-up

operation with low data retention current.

Single 4.5V~5.5V power supply

ꢀ

Operating temperature :

ꢀ

℃

Commercial : 0 ~70

The UT6264C operates from a single 4.5V~5.5V

power supply and all inputs and outputs are fully

TTL compatible.

All inputs and outputs TTL compatible

Fully static operation

ꢀ

Three state outputs

Data retention voltage : 2V (min.)

Package : 28-pin 600 mil PDIP

28-pin 330 mil SOP

PIN CONFIGURATION

Vcc

A12

FUNCTIONAL BLOCK DIAGRAM

CE2

A0-A12

DECODER

MEMORY

ARRAY

A11

Vcc

Vss

A10

CE1

I/O8

I/O7

I/O6

I/O5

I/O4

I/O DATA

CIRCUIT

I/O1-I/O8

COLUMN I/O

I/O1

I/O2

I/O3

Vss

CE1

CE2

PDIP/SOP

CONTROL

CIRCUIT

PIN DESCRIPTION

SYMBOL

DESCRIPTION

A0 - A12

Address Inputs

I/O1 - I/O8

Data Inputs/Outputs

Chip Enable Inputs

Write Enable Input

Output Enable Input

,CE2

CE1

V_CC

V_SS

Power Supply

Ground

No connection

GENERAL DESCRIPTION

UTRON TECHNOLOGY INC.

P80028

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882 FAX: 886-3-5777919

12 3 4 5 6 7...10

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