UTI760A RTS Remote Terminal for Stores
Table I of MIL-STD-883, Method 5004, Class B, also
Standard Military Drawing available
FEATURES
❐ Complete MIL-STD-1760A Notice I through III
❐ Available in 68-pin pingrid array package
remote terminal interface
❐ 1K x 16 of on-chip static RAM for message data,
INTRODUCTION
completely accessible to host
The UT1760A RTS is a monolithic CMOS VLSI solution
totherequirementsofthedual-redundantMIL-STD-1553B
interface as specified by MIL-STD-1760A. Designed to
reduce cost and space in the mission stores interface, the
RTS integrates the remote terminal logic with a user-
configured 1K x 16 static RAM. In addition, the RTS has a
flexible subsystem interface to permit use with most
processors or controllers.
❐ Self-test capability, including continuous loop-back
compare
❐ Programmable memory mapping via pointers for
efficient use of internal memory, including buffering
multiple messages per subaddress
❐ RT-RT Terminal Address Compare
❐ Command word stored with incoming data for
enhanced data management
The RTS provides all protocol, data handling, error
checking, and memory control functions, as well as
comprehensive self-test capabilities. The RTS’s memory
meetsallofamissionstore’smessagestorageneedsthrough
user-defined memory mapping. This memory-mapped
architecture allows multiple message buffering at
❐ User selectable RAM Busy (RBUSY) signal for slow
or fast processor interfacing
❐ Full military operating temperature range, -55°C to
+125°C, screened to the specific test methods listed in
RTA(4:0)
REMOTE TERMINAL
ADDRESS
MCSA(4:0)
CONTROL
INPUTS
MODE CODE/
SUBADDRESS
OUT
STATUS
OUTPUTS
COMMAND
RECOGNITION
CONTROL AND
ERROR LOGIC
DECODER
DECODER
IN
1K X 16 RAM
ADDR(9:0)
OUT
MUX
PTR REGISTER
ENCODER
IN
12MHz
RESET
CLOCK AND RESET
LOGIC
DATA(15:0)
2MHz
Figure 1. UT1760A RTS Functional Block Diagram
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RTS-1