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UPSD3454EVB40T6 PDF预览

UPSD3454EVB40T6

更新时间: 2024-11-18 04:17:55
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意法半导体 - STMICROELECTRONICS 可编程逻辑
页数 文件大小 规格书
293页 4623K
描述
Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic

UPSD3454EVB40T6 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFP包装说明:ROHS COMPLIANT, PLASTIC, LQFP-52
针数:52Reach Compliance Code:unknown
ECCN代码:3A991.A.2HTS代码:8542.31.00.01
风险等级:5.81具有ADC:YES
地址总线宽度:位大小:8
CPU系列:8051最大时钟频率:40 MHz
DAC 通道:NODMA 通道:NO
外部数据总线宽度:JESD-30 代码:S-PQFP-G52
JESD-609代码:e4长度:10 mm
湿度敏感等级:3I/O 线路数量:35
端子数量:52最高工作温度:85 °C
最低工作温度:-40 °CPWM 通道:YES
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP52,.47SQ封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
RAM(字节):32768ROM(单词):262144
ROM可编程性:FLASH座面最大高度:1.6 mm
速度:40 MHz子类别:Microcontrollers
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLERBase Number Matches:1

UPSD3454EVB40T6 数据手册

 浏览型号UPSD3454EVB40T6的Datasheet PDF文件第2页浏览型号UPSD3454EVB40T6的Datasheet PDF文件第3页浏览型号UPSD3454EVB40T6的Datasheet PDF文件第4页浏览型号UPSD3454EVB40T6的Datasheet PDF文件第5页浏览型号UPSD3454EVB40T6的Datasheet PDF文件第6页浏览型号UPSD3454EVB40T6的Datasheet PDF文件第7页 
uPSD34xx  
Turbo Plus Series  
Fast Turbo 8032 MCU with USB and Programmable Logic  
Figure 1.  
Packages  
Features summary  
Fast 8-bit Turbo 8032 MCU, 40 MHz  
– Advanced core, 4-clocks per instruction  
– 10 MIPs peak performance at 40MHz (5V)  
– JTAG Debug and In-System Programming  
TQFP52 (T), 52-lead, Thin, Quad, Flat  
– 16-bit internal instruction path fetches  
double-byte instruction in a single memory  
cycle  
– Branch Cache & 4 instruction Prefetch  
Queue  
– Dual XDATA pointers with automatic  
increment and decrement  
TQFP80 (U), 80-lead, Thin, Quad, Flat  
– Compatible with 3rd party 8051 tools  
Communication interfaces  
Dual Flash memories with memory  
– USB v2.0 Full Speed (12Mbps)  
management  
– Place either memory into 8032 program  
address space or data address space  
– 10 endpoint pairs (In/Out), each endpoint  
with 64-byte FIFO (supports Control, Intr,  
and Bulk transfer types)  
– READ-while-WRITE operation for In-  
Application Programming and EEPROM  
emulation  
– Single voltage program and erase  
– 100K guaranteed erase cycles, 15-year  
retention  
2
– I C Master/Slave controller, 833kHz  
– SPI Master controller, 10MHz  
Two UARTs with independent baud rate  
– IrDA Potocol: up to 115 kbaud  
– Up to 46 I/O, 5V tolerant uPSD34xxV  
Timers and interrupts  
Clock, reset, and power supply management  
– SRAM is Battery Backup capable  
– Three 8032 standard 16-bit timers  
– Programmable Counter Array (PCA), six  
16-bit modules for PWM, CAPCOM, and  
timers  
– 8/10/16-bit PWM operation  
– 12 Interrupt sources with two external  
interrupt pins  
– Flexible 8-level CPU clock divider register  
– Normal, Idle, and Power Down Modes  
– Power-on and Low Voltage reset supervisor  
– Programmable Watchdog Timer  
Programmable logic, general purpose  
– 16 macrocells for logic applications (e.g.,  
shifters, state machines, chip-selects, glue-  
logic to keypads, and LCDs)  
Operating voltage source ( 10%)  
– 5V Devices: 5.0V and 3.3V sources  
– 3.3V Devices: 3.3V source  
A/D converter  
– Eight Channels, 10-bit resolution, 6µs  
July 2006  
Rev 4  
1/293  
www.st.com  
293  

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