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UPSD3233AV-24U6 PDF预览

UPSD3233AV-24U6

更新时间: 2024-01-13 17:08:24
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 闪存微控制器
页数 文件大小 规格书
8页 72K
描述
Flash Programmable System Device with 8032 Microcontroller Core

UPSD3233AV-24U6 技术参数

是否Rohs认证: 符合生命周期:Obsolete
Reach Compliance Code:compliant风险等级:5.84
位大小:8CPU系列:8051
JESD-30 代码:S-PQFP-G80端子数量:80
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP80,.55SQ,20封装形状:SQUARE
封装形式:FLATPACK电源:3.3 V
认证状态:Not QualifiedRAM(字节):256
ROM(单词):131072ROM可编程性:FLASH
速度:24 MHz子类别:Microcontrollers
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD

UPSD3233AV-24U6 数据手册

 浏览型号UPSD3233AV-24U6的Datasheet PDF文件第2页浏览型号UPSD3233AV-24U6的Datasheet PDF文件第3页浏览型号UPSD3233AV-24U6的Datasheet PDF文件第4页浏览型号UPSD3233AV-24U6的Datasheet PDF文件第5页浏览型号UPSD3233AV-24U6的Datasheet PDF文件第6页浏览型号UPSD3233AV-24U6的Datasheet PDF文件第7页 
µPSD3200 FAMILY  
Flash Programmable System Device  
with 8032 Microcontroller Core  
DATA BRIEFING  
FEATURES SUMMARY  
The µPSD3200 Family combines a Flash PSD  
Figure 1. Packages  
architecture with an 8032 microcontroller core  
The µPSD3200 Family of Flash PSDs features  
dual banks of Flash memory, SRAM, general  
purpose I/O and programmable logic, supervi-  
2
sory functions and access via USB, I C, ADC,  
DDC and PWM channels, and an on-board  
8032 microcontroller core, with two UARTs,  
three 16-bit Timer/Counters and one External  
Interrupt. As with other Flash PSD families, the  
µPSD3200 Family is also in-system program-  
mable (ISP) via a JTAG ISP interface.  
Large 8 KByte SRAM with battery back-up  
option  
Dual bank Flash memories  
TQFP52 (T)  
– 128 KByte or 256 KByte main Flash memory  
– 32 KByte secondary Flash memory  
Content Security  
– Block access to Flash memory  
Programmable Decode PLD for flexibleaddress  
mapping of all memories.  
High-speed clock standard 8032 core (12-cycle)  
USB Interface (µPSD3234A-40U6 only)  
2
I C interface for peripheral connections  
TQFP80 (U)  
Five Pulse Width Modulator (PWM) channels  
Standalone Display Data Channel (DDC)  
Six I/O ports with up to 50 I/O pins  
3000 gate PLD with 16 macrocells  
Supervisor functions  
In-System Programming (ISP) via JTAG  
Zero-Power Technology  
Single Supply Voltage  
– 4.5 to 5.5 V  
– 3.0 to 3.6 V  
June 2002  
1/8  
Complete data available on Data-on-Disc CD-ROM or at www.st.com.  

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