UPSD3233AV-24T6

更新时间： 2024-01-03 19:55:19

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		闪存微控制器
页数	文件大小	规格书
8页	72K
描述
Flash Programmable System Device with 8032 Microcontroller Core

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数据手册

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UPSD3233AV-24T6 数据手册

µPSD3200 FAMILY

Table 1. 80-Pin Package Pin Description

Function

Signal Name In/Out

Basic

Alternate

AD7-AD0

A11-A8

I/O

Multiplexed Address/Data bus

External Address Bus

RxD2-RxD1

TxD2-TxD1

INT1-INT0

T2-T0

UART Receive

UART Transmit

Interrupt inputs / timer gate controls

Counter inputs

SDA1-SDA2

SCL1-SCL2

I/O

I C Bus serial data I/O / DDC interface

General I/O port pins

I C Bus clock I/O

VSYNC

T2EX

I/O

VSYNC input for DDC interface

Timer 2 Trigger input

ADC3-ADC0

PWM4-PWM0

USB-, USB+

AVREF

ADC Channels input

8-bit Pulse Width Modulation outputs

USB I/O

Reference Voltage input for ADC

Read signal, external bus

Write signal, external bus

PSEN signal, external bus

Address Latch signal, external bus

Active low reset input

RD_

WR_

PSEN_

ALE

RESET_

XTAL1

Oscillator input pin for system clock

Oscillator output pin for system clock

XTAL2

1. PLD Macro-cell outputs

2. PLD inputs

3. Latched Address Out (A0-A7)

4. Peripheral I/O mode

PA7-PA0

PB7-PB0

I/O

General I/O port pins

1. PLD Macro-cell outputs

2. PLD inputs

3. Latched Address Out (A0-A7)

1. PLD Macro-cell outputs

2. PLD inputs

3. SRAM stand by voltage input (VSTBY)

4. JTAG Interface (TDI, TDO, TMS, TCK, TSTAT,

TERR)

PC7-PC0

I/O

General I/O port pins

5. SRAM battery-on indicator (PC4)

1. PLD I/O

PD2-PD1

I/O

General I/O port pin

2. Clock input to PLD and APD

3. Chip select to PSD Module

Note: PSD Port A and MCU Address/Data bus are added for 80-pin device

4/8

1 2 345 6 7 8

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