Datasheet > UPI-452

UPI-452

更新时间： 2024-02-01 17:23:33

品牌	Logo	应用领域
英特尔 - INTEL		/
页数	文件大小	规格书
53页	499K
描述
CHMOS PROGRAMMABLE I/O PROCESSOR

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UPI-452 数据手册

UPI-452

CHMOS PROGRAMMABLE I/O PROCESSOR

83C452 - 8K 8 Mask Programmable Internal ROM

80C452 - External ROM/EPROM

83C452/80C452:3.5 to 14 MHz Clock

Rate

Two 16-Bit Timer/Counters

Boolean Processor

Software Compatible with the MCS-51

Family

Bit Addressable RAM

8 Interrupt Sources

128-Byte Bi-Directional FIFO Slave

Interface

Programmable Full Duplex Serial

Channel

Two DMA Channels

64K Program Memory Space

64K Data Memory Space

68-Pin PGA and PLCC

256

8-Bit Internal RAM

34 Additional Special Function

Registers

(See Packaging Spec., Order: 231369)

40 Programmable I/O Lines

The Intel UPI-452 (Universal Peripheral Interface) is a 68 pin CHMOS Slave I/O Processor with a sophisticated

bi-directional FIFO buffer interface on the slave bus and a two channel DMA processor on-chip. The UPI-452

is the newest member of Intel’s UPI family of products. It is a general-purpose slave I/O Processor that allows

the designer to grow a customized interface solution.

The UPI-452 contains a complete 80C51 with twice the on-chip data and program memory. The sophisticated

slave FIFO module acts as a buffer between the UPI-452 internal CPU and the external host CPU. To both the

external host and the internal CPU, the FIFO module looks like a bi-directional bottomless buffer that can both

read and write data. The FIFO manages the transfer of data independent of the UPI-452 core CPU and

generates an interrupt or DMA request to either CPU, host or internal, as a FIFO service request.

The FIFO consists of two channels:the Input FIFO and the Output FIFO. The division of the FIFO module

array, 128 bytes, between Input channel and Output channel is programmable by the user. Each FIFO byte

has an additional logical ninth bit to distinguish between a data byte and a Data Stream Command byte.

Additionally, Immediate Commands allow direct, interrupt driven, bi-directional communication between the

UPI-452 internal CPU and external host CPU, bypassing the FIFO.

The on-chip DMA processor allows high speed data transfers from one writeable memory space to another.

As many as 64K bytes can be transferred in a single DMA operation. Three distinct memory spaces may be

used in DMA operations; Internal Data Memory, External Data Memory, and the Special Function Registers

(including the FIFO IN, FIFO OUT, and Serial Channel Special Functions Registers).

*Other brands and names are the property of their respective owners.

Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or

copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make

changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

November 1994

Order Number: 231428-006

12 3 4 5 6 7...53

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UPI5005	EDI	获取价格	MINIBRIDGE 25,40,50 and 60 AMPERE BRIDGE RECTIFIERS
UPI5010	EDI	获取价格	MINIBRIDGE 25,40,50 and 60 AMPERE BRIDGE RECTIFIERS
UPI50100	EDI	获取价格	MINIBRIDGE 25,40,50 and 60 AMPERE BRIDGE RECTIFIERS
UPI50120	EDI	获取价格	MINIBRIDGE 25,40,50 and 60 AMPERE BRIDGE RECTIFIERS
UPI5020	EDI	获取价格	MINIBRIDGE 25,40,50 and 60 AMPERE BRIDGE RECTIFIERS
UPI5040	EDI	获取价格	MINIBRIDGE 25,40,50 and 60 AMPERE BRIDGE RECTIFIERS
UPI5060	EDI	获取价格	MINIBRIDGE 25,40,50 and 60 AMPERE BRIDGE RECTIFIERS
UPI5080	EDI	获取价格	MINIBRIDGE 25,40,50 and 60 AMPERE BRIDGE RECTIFIERS
UPI60	EDI	获取价格	MINIBRIDGE 25,40,50 and 60 AMPERE BRIDGE RECTIFIERS

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