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UPD44645094F5-E50-FQ1-A

更新时间： 2024-01-31 12:32:16
品牌 Logo 应用领域
日电电子 - NEC 静态存储器内存集成电路
页数 文件大小 规格书
40页 379K
描述
QDR SRAM, 8MX9, 0.45ns, CMOS, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165

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UPD44645094F5-E50-FQ1-A 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
针数：165Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.79最大时钟频率 (fCLK)：200 MHz
I/O 类型：SEPARATEJESD-30 代码：R-PBGA-B165
内存密度：75497472 bit内存集成电路类型：STANDARD SRAM
内存宽度：9端子数量：165
字数：8388608 words字数代码：8000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：8MX9
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA165,11X15,40
封装形状：RECTANGULAR封装形式：GRID ARRAY
并行/串行：PARALLEL电源：1.5/1.8,1.8 V
认证状态：Not Qualified最小待机电流：1.7 V
子类别：SRAMs表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：BALL端子节距：1 mm
端子位置：BOTTOMBase Number Matches：1

UPD44645094F5-E50-FQ1-A 数据手册

 浏览型号UPD44645094F5-E50-FQ1-A的Datasheet PDF文件第4页浏览型号UPD44645094F5-E50-FQ1-A的Datasheet PDF文件第5页浏览型号UPD44645094F5-E50-FQ1-A的Datasheet PDF文件第6页浏览型号UPD44645094F5-E50-FQ1-A的Datasheet PDF文件第8页浏览型号UPD44645094F5-E50-FQ1-A的Datasheet PDF文件第9页浏览型号UPD44645094F5-E50-FQ1-A的Datasheet PDF文件第10页 
μPD44645084, 44645094, 44645184, 44645364  
Pin Identification  
(1/2)  
Symbol  
Description  
A
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the  
rising edge of K. All transactions operate on a burst of four words (two clock periods of bus activity). These  
inputs are ignored when device is deselected, i.e., NOP (R# = W# = HIGH).  
Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges of K and K#  
during WRITE operations. See Pin Configurations for ball site location of individual signals.  
x8 device uses D0 to D7.  
D0 to Dxx  
x9 device uses D0 to D8.  
x18 device uses D0 to D17.  
x36 device uses D0 to D35.  
Q0 to Qxx  
Synchronous Data Outputs: Output data is synchronized to the respective C and C# or to K and K# rising edges  
if C and C# are tied HIGH. Data is output in synchronization with C and C# (or K and K#), depending on the R#  
command. See Pin Configurations for ball site location of individual signals.  
x8 device uses Q0 to Q7.  
x9 device uses Q0 to Q8.  
x18 device uses Q0 to Q17.  
x36 device uses Q0 to Q35.  
R#  
Synchronous Read: When LOW this input causes the address inputs to be registered and a READ cycle to be  
initiated. This input must meet setup and hold times around the rising edge of K. If a READ command (R# =  
LOW) is input, an input of R# on the subsequent rising edge of K is ignored.  
Synchronous Write: When LOW this input causes the address inputs to be registered and a WRITE cycle to be  
initiated. This input must meet setup and hold times around the rising edge of K. If a WRITE command (W# =  
LOW) is input, an input of W# on the subsequent rising edge of K is ignored.  
Synchronous Byte Writes (Nibble Writes on x8): When LOW these inputs cause their respective byte or nibble  
to be registered and written during WRITE cycles. These signals must meet setup and hold times around the  
rising edges of K and K# for each of the two rising edges comprising the WRITE cycle. See Pin  
Configurations for signal to data relationships.  
W#  
BWx#  
NWx#  
x8 device uses NW0#, NW1#.  
x9 device uses BW0#.  
x18 device uses BW0#, BW1#.  
x36 device uses BW0# to BW3#.  
See Byte Write Operation for relation between BWx#, NWx# and Dxx.  
Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data  
on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of phase with K. All  
synchronous inputs must meet setup and hold times around the clock rising edges.  
Output Clock: This clock pair provides a user controlled means of tuning device output data. The rising edge of  
C# is used as the output timing reference for first and third output data. The rising edge of C is used as the  
output reference for second and fourth output data. Ideally, C# is 180 degrees out of phase with C. When use of  
K and K# as the reference instead of C and C#, then fixed C and C# to HIGH. Operation cannot be guaranteed  
unless C and C# are fixed to HIGH (i.e. toggle of C and C#).  
K, K#  
C, C#  
Preliminary Data Sheet M18232EJ2V0DS  
7
1...45678910...40

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与UPD44645094F5-E50-FQ1-A相关器件

型号 品牌 描述 获取价格 数据表
UPD44645182F5-E40-FQ1-A NEC QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165

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UPD44645182F5-E50-FQ1 NEC QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, PLASTIC, BGA-165

获取价格
UPD44645182F5-E50-FQ1-A NEC QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165

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UPD44645184F5-E37-FQ1-A NEC QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165

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UPD44645184F5-E37-FQ1-A RENESAS QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, LEAD FREE, PLASTIC, BGA-165

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UPD44645184F5-E50-FQ1 NEC QDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, PLASTIC, BGA-165

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