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UPC4064C-A PDF预览

UPC4064C-A

更新时间: 2024-11-18 21:14:19
品牌 Logo 应用领域
日电电子 - NEC 放大器ISM频段光电二极管
页数 文件大小 规格书
9页 142K
描述
Operational Amplifier, 4 Func, 10000uV Offset-Max, BIPolar, PDIP14, 0.300 INCH, PLASTIC, DIP-14

UPC4064C-A 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:0.300 INCH, PLASTIC, DIP-14Reach Compliance Code:compliant
风险等级:5.78放大器类型:OPERATIONAL AMPLIFIER
最大平均偏置电流 (IIB):0.0001 µA标称共模抑制比:90 dB
最大输入失调电压:10000 µVJESD-30 代码:R-PDIP-T14
JESD-609代码:e6/e4长度:19.22 mm
标称负供电电压 (Vsup):-15 V功能数量:4
端子数量:14最高工作温度:80 °C
最低工作温度:-20 °C封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:5.08 mm
标称压摆率:3 V/us子类别:Operational Amplifier
最大压摆率:1 mA标称供电电压 (Vsup):15 V
表面贴装:NO技术:BIPOLAR
温度等级:COMMERCIAL EXTENDED端子面层:TIN BISMUTH/NICKEL PALLADIUM GOLD
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
标称均一增益带宽:1000 kHz宽度:7.62 mm
Base Number Matches:1

UPC4064C-A 数据手册

 浏览型号UPC4064C-A的Datasheet PDF文件第2页浏览型号UPC4064C-A的Datasheet PDF文件第3页浏览型号UPC4064C-A的Datasheet PDF文件第4页浏览型号UPC4064C-A的Datasheet PDF文件第5页浏览型号UPC4064C-A的Datasheet PDF文件第6页浏览型号UPC4064C-A的Datasheet PDF文件第7页 
DATA SHEET  
BIPOLAR ANALOG INTEGRATED CIRCUIT  
µPC4064  
J-FET INPUT LOW-POWER QUAD OPERATIONAL AMPLIFIER  
DESCRIPTION  
The µPC4064 is a low power J-FET input quad operational amplifier that will operate at voltage levels as low as  
±2 V. Input current is typically less than 1mA. With input bias and offset currents as low as a few pA, the µPC4064 is  
an excellent choice for hand-held measurement equipment.  
FEATURES  
Low supply current: 800 µA (TYP.)  
Very low input bias and offset currents  
High input impedance...J-FET Input Stage  
Low supply voltage operation  
Output short circuit protection  
Internal frequency compensation  
ORDERING INFORMATION  
Part Number  
Package  
µPC4064C  
14-pin plastic DIP (7.62 mm (300))  
14-pin plastic SOP (5.72 mm (225))  
µPC4064G2  
EQUIVALENT CIRCUIT (1/4 Circuit)  
PIN CONFIGURATION (Top View)  
V+  
µ
PC4064C, 4064G2  
R1  
R4  
R9  
Q
9
Q
14  
OUT  
1
1
14 OUT  
4
Q
5
1
4
Q
15  
I
I1  
2
3
4
5
6
7
13 II4  
− +  
− +  
Q
Q
11  
Q
16  
Q
8
Q
12  
I
N1  
12 IN4  
11 V−  
10 IN3  
R8  
I
I
Q
10  
R7  
Q
1
Q
2
V+  
Q
17  
R5  
Q
18  
I
N
C1  
I
N2  
13  
Q
3
Q
4
Q
7
− +  
− +  
I
I2  
9
I
I3  
OUT  
Q20  
2
3
Q
6
Q
19  
OUT  
2
8
OUT  
3
R2  
R3  
R6  
V–  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
Document No. G15166EJ4V0DS00 (4th edition)  
Date Published March 2004 N CP(K)  
Printed in Japan  
1987  
The mark shows major revised points.  

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