Preliminary
uP7718
Functional Description
Output Voltage Programming
Definitions
Figure 1 shows a typical application of 2.5V to 1.8V
conversion with a 5.0V control supply. The output voltage
is sensed through a voltage divider and regulated to internal
reference voltage VREF. The output voltage is programmed
as:
Some important terminologies for LDO are specified below.
Dropout Voltage
The input/output voltage differential at which the regulator
output no longer maintains regulation against further
reductions in input voltage. Measured when the output drops
2% below its nominal value.Dropout voltage is affected by
junction temperature, load current and minimum input
supply requirements.
VOUT = VREF x (R1+R2) / R1 = 0.8V x (22.5k/10k) = 1.8V
It’s recommended to maintain 50-100uA through the output
divider network for a tight load and line regulation. The
internal voltage reference is VREF = 0.8V with 1.5% initial
accuracy. This commands the use of 0.5% or better
accuracy resistors to build a precision power supply.
Line Regulation
The change in output voltage for a change in input voltage.
The measurement is made under conditions of low
dissipation or by using pulse techniques such that average
chip temperature is not significantly affected.
CNTL
EN
POK
VOUT
FB
5VCC
R4
10R
R3
10K
Load Regulation
VOUT
The change in output voltage for a change in load current
at constant chip temperature. The measurement is made
under conditions of low dissipation or by using pulse
techniques such that average chip temperature is not
significantly affected.
R2
12.5K
C4
option
VIN
VIN
C2
4.7uF
C1
1uF
R1
10K
C3
10uF
GND
Maximum Power Dissipation
The maximum total device dissipation for which the
regulator will operate within specifications.
Figure 1. Typical application of 2.5V to 1.8V conversion
with a 5.0V control supply
Quiescent Bias Current
Over Current and Short Circuit Protection
Current which is used to operate the regulator chip and is The uP7718 features a foldback over current protection
not delivered to the load.
function as shown in Figure 2. The current limit threshold
level is proportional to VOUT/VNOM and is typically 5.7Awhen
VOUT = VNOM, where VNOM is the target output voltage. If the
output continuously demands more current than the
maximum current, output voltage will eventually drops below
its nominal value. This, in turns, will lower its OCP threshold
level. This will limit power dissipation in the device when
over current limit happens.
The quiescent current IQ is defined as the supply current
used by the regulator itself that does not pass into the
load. It typically includes all bias currents required by the
LDO and any drive current for the pass transistor.
Initialization
The uP7718 automatically initiates upon the receipt of
supply voltage and power voltage.Apower on reset circuit
continuously monitors VIN and CNTL pins voltages with
rising threshold levels of 0.9V and 2.7V respectively.
When output short circuit occurs, the uP7718 will try to
rebuild the output voltage with maximum allowable current
as shown if Figure 3. The duty cycle is about 5.9% and the
averaged short circuit current is about 450mA.
Chip Enable and Soft Start
The uP7718 features an enable pin for enable/disable
control of the chip. Pulling VEN lower than 0.5V disables
the chip and reduces its quiescent current down to 10uA.
When disabled, an internal MOSFET of 60Ω RDS(ON) turns
on to pull output voltage to ground. Pulling VEN higher than
0.9V enables the output voltage, providing POR is
recognized. The uP7718 features soft start function that
limits inrush current for charging the output capacitors. The
soft start time is typically 1ms.
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP7718-DS-P0000
3
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