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UCX823A PDF预览

UCX823A

更新时间: 2024-11-27 22:17:51
品牌 Logo 应用领域
德州仪器 - TI 控制器
页数 文件大小 规格书
9页 458K
描述
High Speed PWM Controller

UCX823A 数据手册

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UC1823A,B/1825A,B  
UC2823A,B/2825A,B  
UC3823A,B/3825A,B  
High Speed PWM Controller  
FEATURES  
DESCRIPTION  
The UC3823A & B and the UC3825A & B family of PWM control ICs are im-  
proved versions of the standard UC3823 & UC3825 family. Performance en-  
hancements have been made to several of the circuit blocks. Error amplifier gain  
bandwidth product is 12MHz while input offset voltage is 2mV. Current limit  
threshold is guaranteed to a tolerance of 5%. Oscillator discharge current is spec-  
ified at 10mA for accurate dead time control. Frequency accuracy is improved  
to 6%. Startup supply current, typically 100µA, is ideal for off-line applications.  
The output drivers are redesigned to actively sink current during UVLO at no  
expense to the startup current specification. In addition each output is capable  
of 2A peak currents during transitions.  
Improved versions of the  
UC3823/UC3825 PWMs  
Compatible with Voltage or  
Current-Mode Topologies  
Practical Operation at Switching  
Frequencies to 1MHz  
50ns Propagation Delay to Output  
High Current Dual Totem Pole  
Outputs (2A Peak)  
Functional improvements have also been implemented in this family. The  
UC3825 shutdown comparator is now a high-speed overcurrent comparator with  
a threshold of 1.2V. The overcurrent comparator sets a latch that ensures full  
discharge of the soft start capacitor before allowing a restart. While the fault latch  
is set, the outputs are in the low state. In the event of continuous faults, the soft  
start capacitor is fully charged before discharge to insure that the fault frequency  
does not exceed the designed soft start period. The UC3825 Clock pin has be-  
come CLK/LEB. This pin combines the functions of clock output and leading  
edge blanking adjustment and has been buffered for easier interfacing.  
continued  
Trimmed Oscillator Discharge  
Current  
Low 100µA Startup Current  
Pulse-by-Pulse Current Limiting  
Comparator  
Latched Overcurrent Comparator  
With Full Cycle Restart  
BLOCK DIAGRAM  
UDG-95101  
* Note: 1823A,B Version Toggles Q and Q are always low  
9/95  

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