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UCD74111RVFT PDF预览

UCD74111RVFT

更新时间： 2024-02-26 03:51:43
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
22页 843K
描述
High-Current, Synchronous Buck Power Stage

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UCD74111RVFT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：HQCCN, LCC40,.2X.28,20
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：1.69模拟集成电路 - 其他类型：SWITCHING REGULATOR
控制模式：VOLTAGE-MODE控制技术：PULSE WIDTH MODULATION
最大输入电压：14 V最小输入电压：4.7 V
标称输入电压：12 VJESD-30 代码：R-PQCC-N40
JESD-609代码：e4长度：7 mm
湿度敏感等级：2功能数量：1
端子数量：40最高工作温度：125 °C
最低工作温度：-40 °C最大输出电流：15 A
封装主体材料：PLASTIC/EPOXY封装代码：HQCCN
封装等效代码：LCC40,.2X.28,20封装形状：RECTANGULAR
封装形式：CHIP CARRIER, HEAT SINK/SLUG峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.52 mm
子类别：Switching Regulator or Controllers最大供电电流 (Isup)：10 mA
标称供电电压 (Vsup)：12 V表面贴装：YES
切换器配置：BUCK最大切换频率：2000 kHz
温度等级：AUTOMOTIVE端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：5 mmBase Number Matches：1

UCD74111RVFT 数据手册

 浏览型号UCD74111RVFT的Datasheet PDF文件第4页浏览型号UCD74111RVFT的Datasheet PDF文件第5页浏览型号UCD74111RVFT的Datasheet PDF文件第6页浏览型号UCD74111RVFT的Datasheet PDF文件第8页浏览型号UCD74111RVFT的Datasheet PDF文件第9页浏览型号UCD74111RVFT的Datasheet PDF文件第10页 
UCD74111  
www.ti.com  
SLUSAT8 –OCTOBER 2012  
PIN FUNCTIONS (continued)  
PIN  
I/O  
DESCRIPTION  
NAME  
NO.  
13  
14  
15  
16  
17  
18  
19  
20  
PGND  
Power ground pins. These pins provide a return path for low-side FET and the low-side gate driver.  
PWM input. This pin is a digital input that accepts 3.3 V or 5 V logic level signals. A Schmitt trigger input  
comparator desensitizes this pin from external noise. When SRE mode is high, this pin controls both gate  
drivers. When SRE mode is low, this pin only controls the high-side driver. This pin can detect when the input  
drive signal has switched to a high impedance (tri-state) mode. When the high impedance mode is detected,  
both the high-side gate and low-side gate signals are held low.  
PWM  
RDLY  
SRE  
38  
39  
31  
I
I
I
Requires a resistor to AGND for setting the current sense blanking time for the high-side current sense  
comparator and output current limit circuitry.  
Synchronous rectifier enable or low-side input. This pin is a digital input capable of accepting 3.3V or 5V logic  
level signals. A Schmitt trigger input comparator desensitizes this pin from external noise. When SRE mode is  
high, this signal, when low, disables the synchronous rectifier FET. The low-side gate signal is held off. When  
SRE mode is high, this signal, when high, allows the low-side gate signal to function according to the state of  
the PWM pin. When SRE mode is low, this pin is a direct input to the low-side gate driver.  
Synchronous rectifier enable mode select pin. When pulled high to BP3, the high-side and low-side gate drive  
timing is controlled by the PWM pin. Anti-cross-conduction logic prevents simultaneous application of high-side  
and low-side gate drive. When pulled low to AGND, independent operation of the high-side and low-side gate is  
selected. The high-side gate is directly controlled by the PWM signal. The low-side gate is directly controlled by  
the SRE signal. No anti-cross-conduction circuitry is active in this mode. This pin should not be left floating.  
SRE_MD  
30  
I
7
8
9
Sense line for the adaptive anti-cross conduction circuitry. Serves as common connection for the flying high  
side FET driver.  
SW  
I/O  
10  
11  
12  
Input voltage to internal driver circuitry and control circuitry. Connect a low ESR bypass ceramic capacitor of  
100 nF or greater from this pin to AGND.  
VDD  
VGG  
27  
I
Gate drive voltage supply. When VGG_DIS is low, VGG is generated by an on-chip linear regulator. Nominal  
I/O output voltage is 6.4 V. When VGG_DIS is high, an externally supplied gate voltage can be applied to this pin.  
Connect a 4.7 µF low ESR ceramic capacitor from this pin to PGND.  
3
VGG disable pin. When pulled high to BP3, the on-chip VGG linear regulator is disabled. When disabled, an  
VGG_DIS  
2
I
I
externally supplied gate voltage must be connected to the VGG pin. Connect this pin to AGND to use the on-  
chip regulator.  
VIN  
21–26  
Power input to the high-side FET.  
Thermal Pad  
Power Pad for better thermal performance. It is also connected to PGND internally.  
Copyright © 2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
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