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UCD74111RVFT PDF预览

UCD74111RVFT

更新时间： 2024-01-22 09:05:26
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
22页 843K
描述
High-Current, Synchronous Buck Power Stage

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UCD74111RVFT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：HQCCN, LCC40,.2X.28,20
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：1.69模拟集成电路 - 其他类型：SWITCHING REGULATOR
控制模式：VOLTAGE-MODE控制技术：PULSE WIDTH MODULATION
最大输入电压：14 V最小输入电压：4.7 V
标称输入电压：12 VJESD-30 代码：R-PQCC-N40
JESD-609代码：e4长度：7 mm
湿度敏感等级：2功能数量：1
端子数量：40最高工作温度：125 °C
最低工作温度：-40 °C最大输出电流：15 A
封装主体材料：PLASTIC/EPOXY封装代码：HQCCN
封装等效代码：LCC40,.2X.28,20封装形状：RECTANGULAR
封装形式：CHIP CARRIER, HEAT SINK/SLUG峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.52 mm
子类别：Switching Regulator or Controllers最大供电电流 (Isup)：10 mA
标称供电电压 (Vsup)：12 V表面贴装：YES
切换器配置：BUCK最大切换频率：2000 kHz
温度等级：AUTOMOTIVE端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：5 mmBase Number Matches：1

UCD74111RVFT 数据手册

 浏览型号UCD74111RVFT的Datasheet PDF文件第3页浏览型号UCD74111RVFT的Datasheet PDF文件第4页浏览型号UCD74111RVFT的Datasheet PDF文件第5页浏览型号UCD74111RVFT的Datasheet PDF文件第7页浏览型号UCD74111RVFT的Datasheet PDF文件第8页浏览型号UCD74111RVFT的Datasheet PDF文件第9页 
UCD74111  
SLUSAT8 –OCTOBER 2012  
www.ti.com  
DEVICE INFORMATION  
RVF PACKAGE  
40 PINS  
(TOP VIEW)  
40  
39  
38  
37  
36  
35  
34  
33  
1
2
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
AGND  
VGG_DIS  
VGG  
N/C  
ILIM  
SRE  
SRE_MD  
FLT  
3
4
5
BOOT  
N/C  
HS_SNS  
VDD  
VIN  
6
7
SW  
8
SW  
VIN  
9
SW  
VIN  
10  
11  
12  
SW  
VIN  
SW  
VIN  
Thermal Pad  
SW  
VIN  
13  
14  
15  
16  
17  
18  
19  
20  
The thermal pad functions as an electrical ground connection.  
PIN FUNCTIONS  
PIN  
I/O  
DESCRIPTION  
NAME  
NO.  
Analog ground return for all circuits except the low-side gate driver. The analog ground and power ground  
should be connected together at one point, near the AGND pin.  
AGND  
1
Voltage supply to internal control circuitry. Connect a low ESR bypass ceramic capacitor of 100 nF or greater  
from this pin to AGND. Also a resistor of 1Ω to 2Ω must be connected between VGG and this pin.  
AVGG  
BOOT  
BP3  
40  
5
I/O  
Floating bootstrap supply for high side driver. Connect the bootstrap capacitor between this pin and the SW  
I/O node. The bootstrap capacitor provides the charge to turn on the high-side FET. A low ESR ceramic capacitor  
of 220 nF or greater from this pin to SW must be connected.  
Output bypass for the internal 3.3V regulator. Connect a low ESR bypass ceramic capacitor of 1 µF or greater  
from this pin to AGND.  
37  
O
CSN  
CSP  
35  
36  
I
I
Inverting input of the output current sense amplifier and current limit comparator.  
Non-inverting input of the output current sense amplifier and current limit comparator.  
Fault Flag. The FLT signal is a 3.3V digital output which asserts high when an overcurrent, over-temperature,  
or UVLO fault is detected. After the device detects an overcurrent event, the flag resets to low on the falling  
edge of the next pulse, provided the overcurrent condition no longer exists during the on-time of the PWM  
signal. For UVLO and over-temperature faults, the flag is reset when the fault condition no longer exists.  
FLT  
29  
O
HS_SNS  
ILIM  
28  
32  
I
I
A 2-kΩ resistor must be connected from this pin directly to the drain of the high-side FET.  
Output current limit threshold set pin. The voltage on this pin sets the fault threshold voltage on the IMON pin.  
The nominal threshold voltage range is 0.5 V to 3.0 V. When VIMON exceeds VILIM, the FLT pin is asserts and  
the high-side gate pulse truncates.  
Current sense linear amplifier output. The output voltage level on this pin represents the average output  
current. V(IMON) = 0.5 V + 50.2(V(CSP) – V(CSN)).  
IMON  
N/C  
33  
O
4
6
Not internally connected.  
34  
6
Submit Documentation Feedback  
Copyright © 2012, Texas Instruments Incorporated  
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