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UCC5610J

更新时间: 2024-11-22 23:39:07
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描述
Terminator

UCC5610J 数据手册

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UCC5610  
18-Line 3-5 Volt Low Capacitance SCSI Active Terminator  
FEATURES  
DESCRIPTION  
Complies with SCSI, SCSI-2, SCSI-3  
and FAST-20 (Ultra) Standards  
The UCC5610 provides 18 lines of active termination for a SCSI (Small  
Computer Systems Interface) parallel bus. The SCSI standard recom-  
mends active termination at both ends of the cable.  
2.75V to 7V Operation  
The UCC5610 is ideal for high performance 3.3V SCSI systems. The key  
features contributing to such low operating voltage are the 0.1V drop out  
regulator and the 2.75V reference. The reduced reference voltage was  
necessary to accommodate the lower termination current dictated in the  
SCSI-3 specification. During disconnect the supply current is typically  
only 0.5µA, which makes the IC attractive for battery powered systems.  
1.8pF Channel Capacitance during  
Disconnect  
0.5µA Supply Current in Disconnect  
Mode  
110 Ohm/2.5k Programmable  
Termination  
The UCC5610 is designed with an ultra low channel capacitance of  
1.8pF, which eliminates effects on signal integrity from disconnected ter-  
minators at interim points on the bus.  
Completely Meets SCSI Hot Plugging  
-650mA Sourcing Current for  
Termination  
The UCC5610 can be programmed for either a 110 ohm or 2.5k ohm ter-  
mination. The 110 ohm termination is used for standard SCSI bus lengths  
and the 2.5k ohm termination is typically used in short bus applications.  
When driving the TTL compatible DISCNCT pin directly, the 110 ohm ter-  
mination is connected when the DISCNCT pin is driven low, and discon-  
nected when driven high. When the DISCNCT pin is driven through an  
impedance between 80k and 150k, the 2.5k ohm termination is con-  
nected when the DISCNCT pin is driven low, and disconnected when  
+400mA Sinking Current for Active  
Negation Drivers  
Trimmed Termination Current to 4%  
Trimmed Impedance to 7%  
Current Limit and Thermal Shutdown  
Protection  
driven high.  
continued  
BLOCK DIAGRAM  
UDG-94128-1  
Circuit Design Patented  
2/97  
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