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UCC3921DTR/81143 PDF预览

UCC3921DTR/81143

更新时间： 2024-11-20 12:02:35
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
16页 1108K
描述
Latchable Negative Floating Hot Swap Power Manager

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中文翻译

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UCC3921DTR/81143 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP8,.25针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：5.33可调阈值：YES
模拟集成电路 - 其他类型：POWER SUPPLY SUPPORT CIRCUITJESD-30 代码：R-PDSO-G8
JESD-609代码：e4长度：4.9 mm
湿度敏感等级：2信道数量：1
功能数量：1端子数量：8
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP8,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.75 mm
子类别：Power Management Circuits最大供电电流 (Isup)：2 mA
最大供电电压 (Vsup)：10 V最小供电电压 (Vsup)：9 V
标称供电电压 (Vsup)：9.5 V表面贴装：YES
技术：BICMOS温度等级：COMMERCIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
阈值电压标称：2.45处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3.9 mm

UCC3921DTR/81143 数据手册

 浏览型号UCC3921DTR/81143的Datasheet PDF文件第2页浏览型号UCC3921DTR/81143的Datasheet PDF文件第3页浏览型号UCC3921DTR/81143的Datasheet PDF文件第4页浏览型号UCC3921DTR/81143的Datasheet PDF文件第5页浏览型号UCC3921DTR/81143的Datasheet PDF文件第6页浏览型号UCC3921DTR/81143的Datasheet PDF文件第7页 
UCC1921  
UCC2921  
UCC3921  
Latchable Negative Floating Hot Swap Power Manager  
FEATURES  
DESCRIPTION  
• Precision Fault Threshold  
The UCC3921 family of negative floating hot swap power managers pro-  
vides complete power management, hot swap, and fault handling capa-  
bility. The IC is referenced to the negative input voltage and is powered  
through an external resistor connected to ground, which is essentially a  
current drive as opposed to the traditional voltage drive. The onboard  
10V shunt regulator protects the IC from excess voltage and serves as a  
reference for programming the maximum allowable output sourcing cur-  
rent during a fault. All control and housekeeping functions are integrated  
and externally programmable. These include the fault current level, maxi-  
mum output sourcing current, maximum fault time, selection of Retry or  
Latched mode, soft start time, and average power limiting. In the event of  
a constant fault, the internal timer will limit the on time from less than  
0.1% to a maximum of 3% duty cycle. The duty cycle modulation de-  
pends on the current into PL, which is a function of the voltage across  
the FET, thus limiting average power dissipation in the FET. The fault  
level is fixed at 50mV across the current sense amplifier to minimize total  
• Programmable:  
Average Power Limiting, Linear  
Current Control, Overcurrent Limit  
and Fault Time  
• Fault Output Indication Signal  
• Automatic Retry Mode or Latched  
Operation Mode  
• Shutdown Control  
• Undervoltage Lockout  
• 250µs Glitch Filter on the SDFLTCH  
pin  
• 8-Pin DIL and SOIC  
(continued)  
BLOCK DIAGRAM  
UDG-99052  
3/98  
1234567...16

中文翻译

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UCC3921DTR/81143 替代型号

型号 品牌 替代类型 描述 数据表
UCC3921DTR/81143G4 TI

完全替代

 Latchable Negative Floating Hot Swap Power Manager
UCC3921D/81143G4 TI

完全替代

 Latchable Negative Floating Hot Swap Power Manager
UCC3921D/81143 TI

完全替代

 Latchable Negative Floating Hot Swap Power Manager

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