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UCC3583Q

更新时间： 2024-11-28 23:39:03
品牌 Logo 应用领域
其他 - ETC 开关信息通信管理控制器
页数 文件大小 规格书
10页 442K
描述
Current-Mode SMPS Controller

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中文翻译

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UCC3583Q 数据手册

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UCC1583  
UCC2583  
UCC3583  
Switch Mode Secondary Side Post Regulator  
FEATURES  
DESCRIPTION  
• Precision Secondary Side Post  
Regulation for Multiple Output Power  
Supplies  
The UCC3583 is a synchronizable secondary side post regulator for preci-  
sion regulation of the auxiliary outputs of multiple output power supplies. It  
contains a leading edge pulse width modulator, which generates the gate  
drive signal for a FET power switch connected in series with the rectifying  
diode. The turn-on of the power switch is delayed from the leading edge of  
the secondary power pulse to regulate the output voltage. The UCC3583  
contains a ramp generator slaved to the secondary power pulse, a voltage  
error amplifier, a current error amplifier, a PWM comparator and associ-  
ated logic, a gate driver, a precision reference, and protection circuitry.  
• Useful for Both Single Ended and  
Center Tapped Secondary Circuits  
• Ideal Replacement for Complex  
Magnetic Amplifier Regulated Circuits  
• Leading Edge Modulation  
The ramp discharge and termination of the gate drive signal are triggered  
by the synchronization pulse, typically derived from the falling edge of the  
transformer secondary voltage. The ramp starts charging again once its  
low threshold is reached. The gate drive signal is turned on when the ramp  
voltage exceeds the control voltage. This leading edge modulation tech-  
nique prevents instability when the UCC3583 is used in peak current mode  
primary controlled systems.  
• Does Not Require Gate Drive  
Transformer  
• High Frequency (>500kHz) Operation  
• Applicable for Wide Range of Output  
Voltages  
• High Current Gate Driver (0.5A  
The controller operates from a floating power supply referenced to the out-  
put voltage being controlled. It features an undervoltage lockout (UVLO)  
circuit, a soft start circuit, and an averaging current limit amplifier. The cur-  
rent limit can be programmed to be proportional to the output voltage, thus  
achieving foldback operation to minimize the dissipation under short circuit  
conditions.  
Sink/1.5A Source)  
• Average Current Limiting Loop  
(continued)  
TYPICAL APPLICATION AND BLOCK DIAGRAM  
UDG-96201-2  
Note: Pin connections shown for 14-pin packages.  
11/98  
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