UCC27444-Q1
ZHCSPQ0A –MAY 2022 –REVISED JULY 2023
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6.6 Switching Characteristics
Unless otherwise noted, VDD = VEN = 4.5 V to 18 V, TA = TJ = –40°C to 125°C, 1-µF capacitor from VDD to GND, no load
on the output. Typical condition specifications are at 25°C (1)
.
PARAMETER
TEST CONDITIONS
CLOAD = 1.8 nF, 10% to 90%, Vin = 0 V –5 V
CLOAD = 1.8 nF, 90% to 10%, Vin = 0 V –5V
MIN TYP MAX UNIT
tRx
tFx
Rise time
11
7
25
23
ns
ns
Fall time
CLOAD = 1.8 nF, VINx_H of the input rise to 10% of output rise,
Vin = 0 V –5 V, Fsw = 500 kHz, 50% duty cycle
tD1x
tD2x
tD3x
tD4x
Turn-on propagation delay
Turn-off propagation delay
Enable propagation delay
Disable propagation delay
18
30
19
24
33
50
31
52
ns
ns
ns
ns
CLOAD = 1.8 nF, VINx_L of the input fall to 90% of output fall, Vin
= 0 V –5 V, VDD= 5V -18V, Fsw = 500 kHz, 50% duty cycle
CLOAD = 1.8 nF, VENx_H of the enable rise to 10% of output
rise, Vin = 0 V –5 V, Fsw = 500 kHz, 50% duty cycle
CLOAD = 1.8 nF, VENx_L of the enable fall to 90% of output fall,
Vin = 0 V –5 V, Fsw = 500 kHz, 50% duty cycle
Delay matching between
two channels
CLOAD = 1.8 nF, Vin = 0 V –5 V, Fsw = 500 kHz, 50% duty
tM
1
8
5
ns
ns
cycle, INA = INB, |tRA –tRB|, |tFA –tFB
|
tPWmin
Minimum input pulse width
22
CL = 1.8 nF, Vin = 0 V –5 V, Fsw = 500 kHz, Vo > 1.5 V
(1) Switching parameters are not tested in production.
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English Data Sheet: SLUSET2
6
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