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UCC27511A-Q1
SLVSCO2A –AUGUST 2014–REVISED SEPTEMBER 2014
UCC27511A-Q1 Single-Channel High-Speed Low-Side Gate Driver
With 4-A Peak Source and 8-A Peak Sink
1 Features
•
Input Pins Capable of Withstanding –5-V DC
Below GND pin
1
•
•
Qualified for Automotive Applications
•
•
Operating Temperature Range of –40°C to 140°C
6-Pin DBV (SOT-23) Package Option
AEC-Q100 Qualified With the Following Results:
–
Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
2 Applications
–
–
Device HBM ESD Classification Level 2
Device CDM ESD Classification Level C4B
•
•
•
Switch-Mode Power Supplies
DC-to-DC Converters
•
•
•
•
Low-Cost Gate-Driver Device Offering Superior
Replacement of NPN and PNP Discrete Solutions
Companion Gate-Driver Devices for Digital Power
Controllers
4-A Peak Source and 8-A Peak Sink
Asymmetrical Drive
•
•
Solar Power, Motor Control, UPS
Gate Driver for Emerging Wide Band-Gap Power
Devices (such as GaN)
Strong Sink Current Offers Enhanced Immunity
Against Miller Turnon
Split Output Configuration (Allows Easy and
Independent Adjustment of Turnon and Turnoff
Speeds) in the UCC27511A-Q1
3 Description
The UCC27511A-Q1 device is a compact gate driver
that offers superior replacement of NPN and PNP
discrete driver (buffer circuit) solutions. The
UCC27511A-Q1 device is an automotive-grade
single-channel low-side, high-speed gate driver rated
for MOSFETs, IGBTs, and emerging wide-bandgap
power devices such as GaN. The device features fast
rise times, fall times, and propagation delays, making
the UCD27511A-Q1 device suitable for high-speed
applications. The device features 4-A peak source
and 8-A peak sink currents with asymmetrical drive,
boosting immunity against parasitic Miller turnon
effect. The split output configuration enables easy
and independent adjustment of rise and fall times
using only two resistors and eliminating the need for
an external diode.
•
•
•
•
Fast Propagation Delays (13-ns typical)
Fast Rise and Fall Times (9-ns and 7-ns typical)
4.5 to 18-V Single Supply Range
Outputs Held Low During VDD UVLO (Ensures
Glitch-Free Operation at Power Up and Power
Down)
•
•
•
TTL and CMOS Compatible Input-Logic Threshold
(Independent of Supply Voltage)
Hysteretic-Logic Thresholds for High-Noise
Immunity
Dual-Input Design (Choice of an Inverting (IN–
Pin) or Non-Inverting (IN+ Pin) Driver
Configuration)
Device Information(1)
–
Unused Input Pin can be Used for Enable or
Disable Function
PART NUMBER
PACKAGE
BODY SIZE (NOM)
UCC27511A-Q1
SOT-23 (6)
2.90 mm × 1.60 mm
•
•
Output Held Low when Input Pins are Floating
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Input Pin Absolute Maximum Voltage Levels Not
Restricted by VDD Pin Bias Supply Voltage
4 Typical Application Diagrams
Non-Inverting Input
Inverting Input
VDD
VDD
V(SOURCE)
C2
4.5 V to18 V
C2
V(SOURCE)
4.5 V to 18 V
L1
UCC27511A-Q1
L1
D1
UCC27511A-Q1
V(IN+)
6
5
4
IN+
VDD
OUTH
OUTL
1
2
3
VO
D1
Q1
6
5
4
IN+
VDD
1
VO
R1
R2
Q1
IN–
R1
R2
+
V(IN–)
–
IN
OUTH
OUTL
2
3
C1
+
GND
C1
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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