Datasheet > UC3633J

UC3633J

更新时间： 2024-11-23 23:38:55

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
8页	588K
描述
Phase-Locked Loop

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数据手册

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UC3633J 数据手册

UC1633

UC2633

UC3633

Phase Locked Frequency Controller

FEATURES

DESCRIPTION

•

Precision Phase Locked Frequency

The UC1633 family of integrated circuits was designed for use in phase

locked frequency control loops. While optimized for precision speed

control of DC motors, these devices are universal enough for most ap-

plications that require phase locked control. A precise reference fre-

quency can be generated using the device’s high frequency oscillator

and programmable frequency dividers. The oscillator operates using a

broad range of crystals, or, can function as a buffer stage to an external

frequency source.

Control System

•

Crystal Oscillator

Programmable Reference Frequency

Dividers

•

Phase Detector with Absolute Frequency

Steering

The phase detector on these integrated circuits compares the refer-

ence frequency with a frequency/phase feedback signal. In the case of

a motor, feedback is obtained at a hall output of other speed detection

device. This signal is buffered by a sense ampilfier that squares up the

signal as it goes into the digital phase detector. The phase detector re-

sponds proportionally to the phase error between the reference and the

sense amplifier output. This phase detector includes absolute fre-

quency steering to provide maximum drive signals when any frequency

error exists. This feature allows optimum start-up and lock times to be

realized.

•

Digital Lock Indicator

Double Edge Option on the Frequency

Feedback Sensing Amplifier

•

Two High Current Op-Amps

5V Reference Output

Two op-amps are included that can be configured to provide necessary

loop filtering. The outputs of the op-amps will source or sink in excess

of 16mA, so they can provide a low impedence control signal to driving

circuits.

Additional features include a double edge option on the sense amplifier

that can be used to double the loop reference frequency for increased

loop bandwidths. A digital lock signal is provided that indicates when

there is zero frequency error, and a 5V reference output allows DC op-

erating levels to be accurately set.

BLOCK DIAGRAM

4/97

12 3 4 5 6 7 8

中文翻译

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与UC3633J相关器件

型号	品牌	获取价格	描述	数据表
UC3633Q	ETC	获取价格	Analog Phase-Locked Loop
UC3633QTR	ETC	获取价格	Analog Phase-Locked Loop
UC3634	TI	获取价格	Phase Locked Frequency Controller
UC3634DW	TI	获取价格	PLL FREQUENCY SYNTHESIZER, PDSO16
UC3634DWTR	TI	获取价格	PLL FREQUENCY SYNTHESIZER, 10MHz, PDSO16, 0.300 INCH, PLASTIC, SOIC-16
UC3634J	TI	获取价格	PLL FREQUENCY SYNTHESIZER, CDIP16
UC3634N	TI	获取价格	Phase Locked Frequency Controller 16-PDIP 0 to 70
UC3634Q	ETC	获取价格	Analog Phase-Locked Loop
UC3634QTR	ETC	获取价格	Analog Phase-Locked Loop
UC3635	TI	获取价格	Phase Locked Frequency Controller