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UC1845ALQMLV PDF预览

UC1845ALQMLV

更新时间: 2024-11-04 04:27:11
品牌 Logo 应用领域
德州仪器 - TI 开关控制器
页数 文件大小 规格书
24页 720K
描述
CURRENT MODE PWM CONTROLLER

UC1845ALQMLV 数据手册

 浏览型号UC1845ALQMLV的Datasheet PDF文件第2页浏览型号UC1845ALQMLV的Datasheet PDF文件第3页浏览型号UC1845ALQMLV的Datasheet PDF文件第4页浏览型号UC1845ALQMLV的Datasheet PDF文件第5页浏览型号UC1845ALQMLV的Datasheet PDF文件第6页浏览型号UC1845ALQMLV的Datasheet PDF文件第7页 
UC1842/3/4/5  
UC2842/3/4/5  
UC3842/3/4/5  
www.ti.com  
SLUS223CAPRIL 1997REVISED JUNE 2007  
CURRENT MODE PWM CONTROLLER  
FEATURES  
DESCRIPTION  
Optimized For Off-line and DC-to-DC  
Converters  
The UC1842/3/4/5 family of control devices provides  
the necessary features to implement off-line or  
dc-to-dc fixed frequency current mode control  
Low Start-Up Current (<1 mA)  
Automatic Feed Forward Compensation  
Pulse-by-Pulse Current Limiting  
Enhanced Load Response Characteristics  
Under-Voltage Lockout With Hysteresis  
Double Pulse Suppression  
schemes with  
a minimal external parts count.  
Internally implemented circuits include under-voltage  
lockout featuring start up current less than 1 mA, a  
precision reference trimmed for accuracy at the error  
amp input, logic to insure latched operation, a PWM  
comparator which also provides current limit control,  
and a totem pole output stage designed to source or  
sink high peak current. The output stage, suitable for  
driving N-Channel MOSFETs, is low in the off state.  
High Current Totem Pole Output  
Internally Trimmed Bandgap Reference  
500-kHz Operation  
Differences between members of this family are the  
under-voltage lockout thresholds and maximum duty  
cycle ranges. The UC1842 and UC1844 have UVLO  
thresholds of 16 VON and 10 VOFF, ideally suited to  
off-line applications. The corresponding thresholds  
for the UC1843 and UC1845 are 8.4 V and 7.6 V.  
The UC1842 and UC1843 can operate to duty cycles  
approaching 100%. A range of zero to 50% is  
obtained by the UC1844 and UC1845 by the addition  
of an internal toggle flip flop which blanks the output  
off every other clock cycle.  
Low RO Error Amp  
BLOCK DIAGRAM  
V
cc  
7 12  
UVLO  
34 V  
5 V  
REF  
S/R  
8 14  
5
4
9
7
GROUND  
V
REF  
5 V  
50 mA  
2.50 V  
Internal  
BIAS  
VREF  
Good  
Logic  
7
11  
V
C
OSC  
R /C  
T
T
6
10  
T
Error  
Amp  
OUTPUT  
S
2R  
R
5
8
PWM  
LATCH  
2
1
3
3
1
5
V
FB  
R
POWER  
GROUND  
1 V  
CURRENT  
SENSE  
COMP  
COMPARATOR  
CURRENT  
SENSE  
Note 1:  
Note 2:  
A = DIL−8 Pin Number. B = SO−14 and CFP−14 Pin Number.  
Toggle flip flop used only in 1844 and 1845.  
A/B  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 1997–2007, Texas Instruments Incorporated  

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