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UC1635L/883B PDF预览

UC1635L/883B

更新时间： 2024-11-24 14:38:39
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
6页 362K
描述
PLL FREQUENCY SYNTHESIZER, 10MHz, CQCC20, CERAMIC, LCC-20

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中文翻译

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UC1635L/883B 技术参数

生命周期：Obsolete零件包装代码：QLCC
包装说明：CERAMIC, LCC-20针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.83Is Samacsys：N
其他特性：MOTION CONTROL APPLICATIONS模拟集成电路 - 其他类型：PLL FREQUENCY SYNTHESIZER
JESD-30 代码：S-CQCC-N20长度：8.89 mm
功能数量：1端子数量：20
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：QCCN
封装形状：SQUARE封装形式：CHIP CARRIER
认证状态：Not Qualified筛选级别：MIL-STD-883
座面最大高度：2.54 mm最大供电电压 (Vsup)：15 V
最小供电电压 (Vsup)：8 V标称供电电压 (Vsup)：12 V
表面贴装：YES技术：BIPOLAR
温度等级：MILITARY端子形式：NO LEAD
端子节距：1.27 mm端子位置：QUAD
宽度：8.89 mmBase Number Matches：1

UC1635L/883B 数据手册

 浏览型号UC1635L/883B的Datasheet PDF文件第2页浏览型号UC1635L/883B的Datasheet PDF文件第3页浏览型号UC1635L/883B的Datasheet PDF文件第4页浏览型号UC1635L/883B的Datasheet PDF文件第5页浏览型号UC1635L/883B的Datasheet PDF文件第6页 
UC1635  
UC2635  
UC3635  
Phase Locked Frequency Controller  
FEATURES  
DESCRIPTION  
•
Precision Phase Locked Frequency  
The UC1635 family of integrated circuits was designed for use in preci-  
sion speed control of DC motors. An extension to the UC1633 line of  
phase locked controllers, these devices provide access to both of the  
digital phase detector’s inputs, and include a reference frequency di-  
vider output pin. With this added flexibility, this family of controllers can  
be used to obtain phase synchronization of multiple motors.  
Control System  
•
•
Crystal Oscillator  
Programmable Reference Frequency  
Dividers  
•
•
•
Phase Detector with Absolute Frequency  
Steering  
A reference frequency can be generated using the device’s crystal oscil-  
lator and programmable dividers. The oscillator operates using a broad  
range of crystals, or, can function as a buffer stage to an external fre-  
quency source.  
Separate Divider Outputs and Phase  
Detector Input Pins  
Double Edge Option on the Frequency  
Feedback Sensing Amplifier  
The phase detector responds proportionally to the phase error between  
the detector’s minus input pin and the sense amplifier output. This  
phase detector includes absolute frequency steering to provide maxi-  
mum drive signals when any frequency error exists. This feature allows  
optimum start-up and lock times to be realized.  
•
•
Two High Current Op Amps  
5V Reference Output  
Two op-amps are included that can be configured to provide necessary  
loop filtering. The outputs of these op-amps will source or sink in excess  
of 16mA, so they can provide a low impedance control signal to driving  
circuits.  
Additional features include a double edge option on the sense amplifier  
that can be used to double the loop reference frequency for increased  
loop bandwidths. A 5V reference output can be used to accurately set  
DC operating levels.  
BLOCK DIAGRAM  
UDG-92019  
7/97  
123456

中文翻译

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