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U1AFS250-FG256I

更新时间： 2024-11-25 05:55:23

品牌	Logo	应用领域
ACTEL		现场可编程门阵列可编程逻辑
页数	文件大小	规格书
17页	568K
描述
Actel Fusion Mixed-Signal FPGA

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技术参数
数据手册

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U1AFS250-FG256I 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	1 MM PITCH, FBGA-256	Reach Compliance Code：	compliant
风险等级：	5.9	Is Samacsys：	N
JESD-30 代码：	S-PBGA-B256	JESD-609代码：	e0
长度：	17 mm	湿度敏感等级：	3
可配置逻辑块数量：	6144	等效关口数量：	250000
端子数量：	256	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	6144 CLBS, 250000 GATES
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装形状：	SQUARE	封装形式：	GRID ARRAY, LOW PROFILE
峰值回流温度（摄氏度）：	225	可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY
认证状态：	Not Qualified	座面最大高度：	1.68 mm
最大供电电压：	1.575 V	最小供电电压：	1.425 V
标称供电电压：	1.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	TIN LEAD/TIN LEAD SILVER	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	30	宽度：	17 mm
Base Number Matches：	1

U1AFS250-FG256I 数据手册

Preliminary v0.4

Actel Fusion Mixed-Signal FPGAs

for the MicroBlade Advanced Mezzanine Card Solution

• Crystal Oscillator Support (32 kHz to 20 MHz)

Features and Benefits

• Programmable Real-Time Counter (RTC)

• Targeted to Advanced Mezzanine Card (AdvancedMC™)

Designs

• 6 Clock Conditioning Circuits (CCCs) with 1 or 2 Integrated

PLLs

• Designed in Partnership with MicroBlade

• 8051-Based Module Management Controller (MMC)

• Fully Compliant with PICMG AMC.0.R2.0 and IPMI v2.0

Specifications

– Phase Shift, Multiply/Divide, and Delay Capabilities

– Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz

Low Power Consumption

• Single 3.3 V Power Supply with On-Chip 1.5 V Regulator

• Sleep and Standby Low Power Modes

• AdvancedMC Reference Design and Starter Kit

High-Performance Reprogrammable Flash

In-System Programming (ISP) and Security

Technology

• Secure ISP with 128-Bit AES via JTAG

• Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process

• Nonvolatile, Retains Program when Powered Off

• Live at Power-Up (LAPU) Single-Chip Solution

• 350 MHz System Performance

• FlashLock to Secure FPGA Contents

Advanced Digital I/O

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages – Up to 5 Banks per Chip

Embedded Flash Memory

• Single-Ended

I/O

Standards:

LVTTL,

LVCMOS

• User Flash Memory – 2 Mbits to 8 Mbits

– Configurable 8-, 16-, or 32-Bit Datapath

– 10 ns Access in Read-Ahead Mode

• 1 kbit of Additional FlashROM

3.3 V / 2.5 V /1.8 V / 1.5 V, 3.3 V PCI

LVCMOS 2.5 V / 5.0 V Input

/ 3.3 V PCI-X, and

• Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS

– Built-In I/O Registers

– 700 Mbps DDR Operation

• Hot-Swappable I/Os

Integrated A/D Converter (ADC) and Analog I/O

• Up to 12-Bit Resolution and up to 600 ksps

• Internal 2.56 V or External Reference Voltage

• ADC: Up to 30 Scalable Analog Input Channels

• High-Voltage Input Tolerance: –10.5 V to +12 V

• Current Monitor and Temperature Monitor Blocks

• Up to 10 MOSFET Gate Driver Outputs

– P- and N-Channel Power MOSFET Support

– Programmable 1, 3, 10, 30 µA and 20 mA Drive Strengths

• ADC Accuracy is Better than 1%

• Programmable Output Slew Rate, Drive Strength, and Weak

Pull-Up/Down Resistor

• Pin-Compatible Packages across the Fusion Family

SRAMs and FIFOs

• Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (×1, ×2, ×4, ×9,

and ×18 organizations available)

• True Dual-Port SRAM (except ×18)

• Programmable Embedded FIFO Control Logic

On-Chip Clocking Support

• Internal 100 MHz RC Oscillator (accurate to 1%)

MicroBlade Fusion Solutions

Fusion Devices

U1AFS25

U1AFS600

U1AFS1500

System Gates

250,000

6,144

Yes

600,000

13,824

Yes

1,500,000

38,400

Yes

Tiles (D-flip-flops)

General Information Secure (AES) ISP

PLLs

Globals

Flash Memory Blocks (2 Mbits)

Total Flash Memory Bits

2 M

1 k

4 M

1 k

8 M

1 k

Memory

FlashROM Bits

RAM Blocks (4,608 bits)

RAM kbits

108

270

Analog Quads

Analog Input Channels

Gate Driver Outputs

I/O Banks (+ JTAG)

Maximum Digital I/Os

Analog I/Os

Analog and I/Os

114

172

252

Notes:

1. Refer to the CoreMP7 datasheet for more information.

2. Refer to the Cortex-M1 product brief for more information.

October 2008

12 3 4 5 6 7...17

中文翻译

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与U1AFS250-FG256I相关器件

型号	品牌	获取价格	描述	数据表
U1AFS250-FG256Y	MICROSEMI	获取价格	Field Programmable Gate Array,
U1AFS250-FG256YI	MICROSEMI	获取价格	Field Programmable Gate Array,
U1AFS250-FGG256	ACTEL	获取价格	Actel Fusion Mixed-Signal FPGA
U1AFS250-FGG256I	ACTEL	获取价格	Actel Fusion Mixed-Signal FPGA
U1AFS250-FGG256Y	MICROSEMI	获取价格	Field Programmable Gate Array,
U1AFS250-FGG256YI	MICROSEMI	获取价格	Field Programmable Gate Array,
U1AFS600	MICROSEMI	获取价格	Fusion Family of Mixed Signal FPGAs
U1AFS600-1FG484YC	MICROSEMI	获取价格	FPGA
U1AFS600-1FG484YI	MICROSEMI	获取价格	FPGA
U1AFS600-1FGG256	MICROSEMI	获取价格	Field Programmable Gate Array,

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