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TZA3054AHN PDF预览

TZA3054AHN

更新时间: 2024-01-30 14:16:30
品牌 Logo 应用领域
恩智浦 - NXP ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
32页 156K
描述
IC SPECIALTY TELECOM CIRCUIT, PQCC20, 4 X 3 MM, 0.85 MM HEIGHT, PLASTIC, SOT-797-1, HVQFN-20, Telecom IC:Other

TZA3054AHN 技术参数

生命周期:Transferred包装说明:,
Reach Compliance Code:unknown风险等级:5.71
Base Number Matches:1

TZA3054AHN 数据手册

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TZA3054A  
100 Mbit/s to 3.2 Gbit/s A-rate limiting amplifier  
Rev. 01 — 12 August 2004  
Objective data sheet  
1. General description  
The TZA3054A is a highly sensitive A-rate™ Limiting amplifier featuring ACE (Automatic  
Current Engine) functionality, Logarithmic Level Detect (LLD), Loss-of-Signal (LOS)  
detector and output jam function. The ACE functionality provides a limiting amplifier which  
achieves optimum performance (sensitivity, bandwidth, jitter and output eye pattern) for  
any bit rate with very low power consumption. This is achieved through automatic  
adjustment of the input bandwidth and the output slew rate by using built-in performance  
monitors. Manual adjustment is possible by programming the I2C-bus registers.  
The integrated I2C-bus controller allows for flexible configuration with a microcontroller,  
which minimizes the number of external connections and external components needed.  
Adjustment of the LOS threshold can be done either via the I2C-bus or with an external  
resistor. The output amplitude is selectable between a high or low value, or adjustable via  
the I2C-bus. The detected logarithmic signal level is indicated directly by a voltage on pin  
LLD, or by a binary value of an I2C-bus register. Furthermore, the junction temperature,  
the internal supply voltage and an external voltage can all be monitored through a built-in  
Analog-to-Digital Converter (ADC) which supports several diagnostic functions.  
These features make the TZA3054A ideally suited for application in modules, including  
Small Form Factor (SFF/SFP/iSFP) modules.  
The TZA3054A comes in a compact 3 × 4 mm2 HVQFN20 package, with the exposed die  
pad serving as the main ground connection.  
2. Features  
A-rate limiting amplifier; supporting any data rate between 100 Mbit/s and 3.2 Gbit/s,  
including data rates such as OC3, OC48, FC, 2FC and GE  
Very low power  
I2C-bus programmable  
Highly sensitive data input with 2.5 mV sensitivity  
On-chip DC offset compensation without external capacitor  
Automatic bandwidth and slew rate adjustment (ACE)  
Pin selectable output level, 500 mV or 1500 mV (p-p) differential  
Rise and fall times 40 ps typical at 3.2 Gbit/s  
Deterministic Jitter typically below 10 ps (p-p)  
Logarithmic Level Detect (LLD) from 1 mV to 1200 mV  
Input amplitude related Loss Of Signal (LOS) indicator with adjustable threshold  
2.9 V to 3.5 V supply voltage  
SFF-8074i and SFF-8472 compliant  

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