Features
H PowerPC single issue integer core.
H Precise exception model.
H Extensive system development support
- on-chip watchpoints and breakpoints,
- program flow tracking,
- On-chip emulation (OnCE) development interface.
H High performance (Dhrystone 2.1: 52 MIPS @ 50 MHz, 3.3V, 1.3 Watts total power).
H Low power (< 241 mW @25 MHz, 2.4 V internal, 3.3 V I/O-core, caches, MMUs, I/O).
H MPC8XX PowerPC system interface, including a periodic interrupt timer, a bus monitor, and
real-time clocks.
H Single Issue, 32-Bit Version of the Embedded PowerPC Core (fully Compatible with Book 1 of
the PowerPC Architecture Definition) with 32 X 32 – Bit Fixed Point Registers
– Embedded PowerPC PerformsBranchFolding, BranchPredictionwithConditionalPrefetch,
without Conditional Execution
TSPC860
32 BIT QUAD INTEGRATED
– 4 Kbyte Data Cache and 4 Kbyte Instruction Cache, Each with an MMU
– Instruction and Data Caches are two way, Set Associative, Physical Address, 4 Word Line
Burst, Least Recently Used (LRU) Replacement, Lockable On-Line Granularity
– MMUs with 32 Entry TLB, Fully associative Instruction and Data TLBs
– MMUs Support Multiple Page Sizes of 4kB, 16 kB, 256 KB, 512 KB and 8 MB ; 16 Virtual
Address Spaces and 8 Protection Groups
POWER QUICCTM
COMMUNICATION
CONTROLLER
– Advanced On-Chip-Emulation Debug Mode
PRELIMINARY
SPECIFICATION
beta SITE
H Up to 32-bit Data Bus
(Dynamic Bus Sizing for 8 and 16 bits).
H 32 Address Lines
H Fully Static Design.
H VCC = +3.3 V± 5 % .
H fmax = 66 MHz (80 MHZ tbc)
H Military temperature range : –55°C < TC < +125°C.
H PD = 0.75 W typical @ 66 MHz
H ATM SAR support available on TSPC860SR version
Description
The TSPC860 PowerPCt QUad Integrated Communication Controller (Power QUICCt) is a
versatile one-chip integrated microprocessor and peripheral combination that can be used in a
variety of controller applications. It particularly excels in communications and networking sys-
tems. The Power QUICC (pronounced ”quick”) can be described as a PowerPC-based derivative
of TS68EN360 (QUICCt).
The CPU on the TSPC860 is a 32-bit PowerPC implementation that incorporates memory man-
agement units (MMUs) and instruction and data caches. The communications processormodule
(CPM)oftheTS68EN360QUICChasbeenenhancedwiththeadditionoftheinterprocessor-inte-
gratedcontroller(I2C) channel. Moderate to high digital signal processing (DSP) functionality has
been added to the CPM. The memory controller has been enhanced, enabling the TSPC860 to
support any type of memory, including high performance memories and newer dynamic random
access memories (DRAMs). Overall system functionality is completed with the addition of a
PCMCIA socket controller supporting up to two sockets and a real-time clock.
PBGA 357
ZP suffix
Screening / Quality
This product will be manufactured in full compliance with :
H Or according to ATMEL-Grenoble standard.
August 2000
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