Datasheet > TSPC603EMGU3LN

TSPC603EMGU3LN

更新时间： 2023-01-02 23:59:45

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
38页	632K
描述
RISC Microprocessor, 32-Bit, 100MHz, CMOS, CBGA255, CERAMIC, BGA-255

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TSPC603EMGU3LN 数据手册

TSPC603E

3. SIGNAL DESCRIPTION

Figure 4, Table 3 and Table 4 describe the signal on the TSPC603e and indicate signal functions. The test signals, TRST, TMS, TCK,

TDI and TDO, comply with subset P-1149.1 of the IEEE testability bus standard.

The 3 signals LSSD_MODE, LI_TSTCLK and L2_TSTCLK are test signals for factory use only and must be pulled up to VDD for

normal machine operations.

DBG

DBWO

DBB

ADDRESS

ARBITRATION

DATA

ATTRIBUTION

ABB

ADDRESS

START

DH[0-31], DL[0-31]

DP[0-7]

DATA

TRANSFER

DPE

A[0-31]

DBDIS

ADDRESS

BUS

AP[0-3]

APE

DRTRY

TEA

DATA

TERMINATION

TT[0-4]

TBST

TSIZ[0-2]

INT, SMI

MCP

GBL

INTERRUPTS

CHECKSTOPS

RESET

TRANSFER

ATTRIBUTE

CKSTP_IN, CKSTP_OUT

HRESET, SRESET

CSE[0-1]

TC[0-1]

RSRV

QREQ, QACK

TBEN

PROCESSOR

STATUS

TLBISYNC

AACK

ADDRESS

TERMINATION

ARTRY

TRST, TCK, TMS, TDI, TD0

JTAG/COP

INTERFACE

SYSCLK

LSSD_MODE,

L1_TSTCLK, L2_TSTCLK

CLK_OUT

LSSD TEST

CONTROL

CLOCKS

PLL_CFG[0-3]

VDD

(20) 13

(19) 23

OVDD

GND*

POWER SUPPLY

(40)

{

OGND*

AVDD

(*) Ground inputs not separated on CBGA package

(number) Pin number in CBGA package

Figure 4 : Functional signal groups

Table 3 : Address and data bus signal index

Signal function

Signal name

Address bus

Data bus

Mnemonic

A[0-31]

Signal

type

if output, physical address of data to be transferred.

if input, represents the physical address of a snoop operation.

I/O

DH[0-31]

DL[0-31]

Represents the state of data, during a data write operation if output, or

during a data read operation if input.

Data bus

Represents the state of data, during a data write operation if output, or

during a data read operation if input.

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