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TSPC603EMA4LN PDF预览

TSPC603EMA4LN

更新时间: 2024-11-26 09:54:51
品牌 Logo 应用领域
爱特美尔 - ATMEL /
页数 文件大小 规格书
38页 632K
描述
RISC Microprocessor, 32-Bit, 120MHz, CMOS, CQFP240, CERAMIC, QFP-240

TSPC603EMA4LN 数据手册

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TSPC603E  
PowerPC 603e RISC MICROPROCESSOR Family  
PID6-603e Specification  
DESCRIPTION  
ThePID6-603eimplementationofPC603e(afternamed603e)  
is a low-power implementation of reduced instruction set com-  
puter (RISC) microprocessors PowerPC family. The 603e  
implements 32-bit effective addresses, integer data types of 8,  
16 and 32 bits, and floating-point data types of 32 and 64 bits.  
The 603e is a low-power 3.3-volt design and provides four soft-  
ware controllable power-saving modes.  
CERQUAD 240  
The 603e is a superscalar processor capable of issuing and  
retiring as many as three instructions per clock. Instructions  
can execute out of order for increased performance ; however,  
the 603e makes completion appear sequential. The 603e inte-  
grates five execution units and is able to execute five instruc-  
tions in parallel.  
The 603e provides independent on-chip, 16-Kbyte, four-way  
set-associative, physically addressed caches for instructions  
and data and on-chip instruction and data memory manage-  
ment units (MMUs). The MMUs contain 64-entry, two-way set-  
associative, data and instruction translation lookaside buffers  
that provide support for demand-paged virtual memory  
address translation and variable-sized block translation.  
A suffix  
CERQUAD 240  
Ceramic Leaded Chip Carrier  
The 603e has a selectable 32 or 64-bit data bus and a 32-bit  
address bus. The 603e interface protocol allows multiple mas-  
ters to complete for system resources through a central exter-  
nal arbiter. The 603e supports single-beat and burst data  
transfers for memory accesses, and supports memory-  
mapped I/O.  
The603eusesanadvanced, 3.3-VCMOSprocesstechnology  
and maintains full interface compatibility with TTL devices.  
The 603e integrates in system testability and debugging fea-  
tures through JTAG boundary-scan capability.  
MAIN FEATURES  
G suffix  
CBGA 255  
Ceramic Ball Grid Array  
H 2.4 SPECint95, 2.1 SPECfp95 @ 100 MHz (estimated)  
H Superscalar (3 instructions per clock peak).  
H Dual 16KB caches.  
H Selectable bus clock.  
H 32-bit compatibility PowerPC implementation.  
H On chip debug support.  
H PD typical = 3.2 Watts (100 MHz), full operating conditions.  
H Nap, doze and sleep modes for power savings.  
H Branch folding.  
H 64-bit data bus (32-bit data bus option).  
H 4-Gbyte direct addressing range.  
SCREENING / QUALITY / PACKAGING  
This product is manufactured in full compliance with :  
H MIL-STD-883 class B or According to TCS standards  
H Upscreenings based upon TCS standards  
H Pipelined single/double precision float unit.  
IEEE 754 compatible FPU.  
H IEEE P 1149-1 test mode (JTAG/C0P).  
H fint max = 100/120/133 MHz.  
H fbus max = 66 MHz.  
H Full military temperature range (Tc = -55°C, Tc = +125°C)  
Industrial temperature range (Tc = 40°C, Tc = +110°C)  
H VCC = 3.3 V ± 5 %.  
H Compatible CMOS input  
H 240 pin Cerquad or 255 pin CBGA packages  
TTL Output.  
December1998  
1/38  

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