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TSPC106AMGU/T83CE PDF预览

TSPC106AMGU/T83CE

更新时间: 2024-11-18 14:36:27
品牌 Logo 应用领域
爱特美尔 - ATMEL 时钟ATM异步传输模式PC外围集成电路
页数 文件大小 规格书
40页 337K
描述
PCI Bus Controller, CMOS, CBGA303, 21 X 25 MM, 3.16 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-303

TSPC106AMGU/T83CE 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:BGA包装说明:BGA, BGA303,19X16,50
针数:303Reach Compliance Code:unknown
ECCN代码:3A001.A.2.CHTS代码:8542.31.00.01
风险等级:5地址总线宽度:32
总线兼容性:60X; POWERPC 601; POWERPC 603; POWERPC 604最大时钟频率:83.3 MHz
外部数据总线宽度:64JESD-30 代码:R-CBGA-B303
JESD-609代码:e0长度:25 mm
端子数量:303最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:BGA封装等效代码:BGA303,19X16,50
封装形状:RECTANGULAR封装形式:GRID ARRAY
电源:3.3 V认证状态:Not Qualified
座面最大高度:3.16 mm子类别:Memory Controllers
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
宽度:21 mmuPs/uCs/外围集成电路类型:BUS CONTROLLER, PCI
Base Number Matches:1

TSPC106AMGU/T83CE 数据手册

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Features  
Processor Bus Frequency Up to 66 MHz and 83.3 MHz  
64-bit Data Bus and 32-bit Address Bus  
L2 Cache Control for 256-Kbyte, 512-Kbyte, 1-Mbyte Sizes  
Provides Support for Either Asynchronous SRAM, Burst SRAM  
or Pipelined Burst SRAM  
Compliant with PCI Specification, Revision 2.1  
PCI Interface Operates at 20 to 33 MHz, 3.3V/5.0V-compatible  
IEEE 1149.1-compliant, JTAG Boundary-scan Interface  
PD Max = 1.7 Watts (66 MHz), Full Operating Conditions  
Nap, Doze and Sleep Modes Reduce Power Consumption  
Fully Compliant with MIL-STD-883 Class Q or According to Atmel Standards  
Upscreenings Based on Atmel Standards  
Full Military Temperature Range (-55°C TC +125°C)  
– Industrial Temperature Range (-40°C TC +110°C)  
VCC = 3.3V 5%  
PCI Bridge/  
Memory  
Controller  
Available in a 303-ball CBGA or a 303-ball CBGA with Solder Column Interposer (SCI)  
(CI-CGA) Package  
TSPC106  
Description  
The TSPC106 provides an integrated, high-bandwidth, high-performance, TTL-com-  
patible interface between a 60x processor, a secondary (L2) cache or up to a total of  
four additional 60x processors, the PCI bus and main memory.  
PCI support allows system designers to rapidly design systems using peripherals  
already designed for PCI.  
The TSPC106 uses an advanced 3.3V CMOS-process technology and maintains full  
interface compatibility with TTL devices.  
The TSPC106 integrates system testability and debugging features via JTAG bound-  
ary-scan capability.  
GS suffix  
CI CGA 303  
G suffix  
CBGA 303  
Ceramic Ball Grid Array  
Ceramic Ball Grid Array  
with Solder Column Interposer (SCI)  
Rev. 2102BHIREL02/02  

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