Datasheet > TSL1401R

TSL1401R

更新时间： 2024-02-03 15:04:46

品牌	Logo	应用领域
其他 - ETC		传感器
页数	文件大小	规格书
10页	120K
描述
128 】 1 LINEAR SENSOR ARRAY WITH HOLD

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技术参数
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TSL1401R 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Transferred	Reach Compliance Code：	unknown
风险等级：	5.71	阵列类型：	LINEAR
主体宽度：	6.35 mm	主体长度或直径：	10.92 mm
动态范围：	72 dB	水平像素：	1
外壳：	PLASTIC	安装特点：	THROUGH HOLE MOUNT
最大工作电流：	4.5 mA	最高工作温度：	70 °C
最低工作温度：		输出范围：	1.60-2.40V
输出类型：	ANALOG VOLTAGE	封装形状/形式：	RECTANGULAR
像素大小：	55.5X63.5 µm	电源：	5 V
传感器/换能器类型：	IMAGE SENSOR,CCD	光谱响应 (nm)：	300-1100
子类别：	CCD Image Sensors	最大供电电压：	5.5 V
最小供电电压：	3 V	表面贴装：	NO
端接类型：	SOLDER	垂直像素：	128
Base Number Matches：	1

TSL1401R 数据手册

TSL1401R

128 × 1 LINEAR SENSOR ARRAY WITH HOLD

TAOS035B – AUGUST 2002

Terminal Functions

TERMINAL

DESCRIPTION

NAME

NO.

Analog output.

CLK

GND

Clock. The clock controls charge transfer, pixel output, and reset.

Ground (substrate). All voltages are referenced to the substrate.

No internal connection.

6, 7

5, 8

Serial input. SI defines the start of the data-out sequence.

Supply voltage. Supply voltage for both analog and digital circuits.

Detailed Description

The sensor consists of 128 photodiodes arranged in a linear array. Light energy impinging on a photodiode

generates photocurrent, which is integrated by the active integration circuitry associated with that pixel.

During the integration period, a sampling capacitor connects to the output of the integrator through an analog

switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity and the

integration time.

The output and reset of the integrators is controlled by a 128-bit shift register and reset logic. An output cycle

is initiated by clocking in a logic 1 on SI. For proper operation, after meeting the minimum hold time condition,

SI must go low before the next rising edge of the clock. An internal signal, called Hold, is generated from the

rising edge of SI and transmitted to analog switches in the pixel circuit. This causes all 128 sampling capacitors

to be disconnected from their respective integrators and starts an integrator reset period. As the SI pulse is

clocked through the shift register, the charge stored on the sampling capacitors is sequentially connected to a

charge-coupled output amplifier that generates a voltage on analog output AO. Simultaneously, during the first

18 clock cycles, all pixel integrators are reset, and the next integration cycle begins on the 19th clock. On the

129th clock rising edge, the SI pulse is clocked out of the shift register and the analog output AO assumes a

high impedance state. Note that this 129th clock pulse is required to terminate the output of the 128th pixel, and

return the internal logic to a known state. A subsequent SI pulse may be presented as early as the 130th clock

pulse, thereby initiating another pixel output cycle.

AO is an op amp-type output that does not require an external pull-down resistor. This design allows a rail-to-rail

output voltage swing. With V_DD= 5 V, the output is nominally 0 V for no light input, 2 V for normal white level, and 4.8 V

for saturation light level. When the device is not in the output phase, AO is in a high-impedance state.

The voltage developed at analog output (AO) is given by:

V_out= V_drk+ (R_e) (E_e)(t_int

)

where:

V_out

is the analog output voltage for white condition

is the analog output voltage for dark condition

is the device responsivity for a given wavelength of light given in V/(µJ/cm²)

is the incident irradiance in µW/cm²

V_drk

R_e

E_e

t_int

is integration time in seconds

A 0.1 µF bypass capacitor should be connected between V and ground as close as possible to the device.

The TSL1401R is intended for use in a wide variety of applications, including: image scanning, mark and code

reading, optical character recognition (OCR) and contact imaging, edge detection and positioning, and optical

linear and rotary encoding.

The LUMENOLOGYr Company

www.taosinc.com

123 4 5 6 7...10

中文翻译

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