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TSC21020F-20MBHXXX PDF预览

TSC21020F-20MBHXXX

更新时间: 2024-11-23 15:55:07
品牌 Logo 应用领域
爱特美尔 - ATMEL 时钟外围集成电路
页数 文件大小 规格书
37页 483K
描述
Floating Point Processor, 40-Bit, CMOS, CQFP256, CERAMIC, MQFP-256

TSC21020F-20MBHXXX 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:QFF,针数:256
Reach Compliance Code:unknownECCN代码:3A001.A.2.C
HTS代码:8542.39.00.01风险等级:5.56
边界扫描:NO最大时钟频率:20 MHz
外部数据总线宽度:40JESD-30 代码:S-CQFP-F256
长度:37.085 mm低功率模式:NO
端子数量:256最高工作温度:125 °C
最低工作温度:-55 °C输出数据总线宽度:40
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QFF
封装形状:SQUARE封装形式:FLATPACK
认证状态:Not Qualified座面最大高度:3.18 mm
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:FLAT端子节距:0.508 mm
端子位置:QUAD总剂量:100k Rad(Si) V
宽度:37.085 mmuPs/uCs/外围集成电路类型:DSP PERIPHERAL, FLOATING POINT PROCESSOR
Base Number Matches:1

TSC21020F-20MBHXXX 数据手册

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TSC21020F  
Radiation Tolerant 32/40–Bit IEEE Floating–Point  
DSP Microprocessor  
Introduction  
Atmel is manufacturing a radiation tolerant version of the The product is pin and code compatible with ADI  
Analog Devices ADSP–21020 32/40–Bit Floating–Point product, making system development straight forward  
DSP.  
and cost effective, using existing development tools and  
algorithms.  
Features  
D Superscalar IEEE Floating-Point-Processor  
D Off-Chip Harvard Architecture Maximizes Signal Processing  
Performance  
D Multiply with Add & Subtract for FFT Butterfly  
Computation  
D Efficient Program Sequencing with Zero-Overhead  
D 50 ns, 20 MIPS Instruction Rate, Single-Cycle Execution  
D 60 MFLOPS Peak, 40 MFLOPS Sustained Performance  
D 1024-Point Complex FFT Benchmark : 0.975 ms  
D Divide (y/x) : 300 ns  
Looping : Single-Cycle Loop Setup  
D Single-Cycle Register File Context Switch  
D 23 ns External RAM Access Time for Zero-Wait-State, 40 ns  
Instruction Execution  
D Inverse Square Root (1/x) : 450 ns  
D IEEE JTAG Standard 1149.1 Test Access Port and On-Chip  
D 32-Bit Single-Precision and 40-Bit Extended-Precision  
Emulation Circuitry  
IEEE Floating-Point Data Formats  
D 223 CPGA package for breadboarding  
D 256 Multi layer quad flat pack, flat leads, for flight models  
D Full compatible with Analog Devices ADSP-21020  
D Latch up immune  
D 32-Bit Fixed-Point Formats, Integer and Fractional, with  
80-Bit Accumulators  
D IEEE Exception Handling with Interrupt on Exception  
D Three Independent Computation Units : Multiplier, ALU,  
and Barrel Shifter  
D Dual Data Address Generators with Indirect, Immediate,  
Modulo, and Bit Reverse Addressing Modes  
D Two Off-Chip Memory Transfers in Parallel with Instruction  
Fetch and Single-Cycle Multiply & ALU Operations  
D Total dose better than 100 Krad (Si)  
D SEU immunity better than 50 MeV/mg/cm2  
D For 25 MHz specification, call factory  
– Design using patent from INPG–CNRS Denis BESSOT / Raoul VELAZCO  
– Product licensed from Analog Devices Inc.  
1
Rev. E – Oct. 05, 1998  

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