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TSB43DB42GHC PDF预览

TSB43DB42GHC

更新时间： 2024-11-20 03:26:23
品牌 Logo 应用领域
德州仪器 - TI 驱动器微控制器和处理器串行IO控制器通信控制器外围集成电路电子数据传输PC时钟
页数 文件大小 规格书
7页 200K
描述
IEEE 1394a-2000 CONSUMER ELECTRONICS SOLUTION

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TSB43DB42GHC 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：LBGA,针数：196
Reach Compliance Code：compliantECCN代码：3A991.A.2
HTS代码：8542.31.00.01风险等级：5.86
地址总线宽度：32总线兼容性：PCI
最大时钟频率：33 MHz最大数据传输速率：400 MBps
驱动器接口标准：IEEE1394; IEEE1394A外部数据总线宽度：32
JESD-30 代码：S-PBGA-B196JESD-609代码：e0
长度：15 mm湿度敏感等级：3
端子数量：196封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装形状：SQUARE
封装形式：GRID ARRAY, LOW PROFILE峰值回流温度（摄氏度）：220
认证状态：Not Qualified座面最大高度：1.5 mm
表面贴装：YES技术：CMOS
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：15 mm
uPs/uCs/外围集成电路类型：PCI BUS CONTROLLERBase Number Matches：1

TSB43DB42GHC 数据手册

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TSB43DA42, TSB43DB42  
www.ti.com  
SLLS560–FEBRUARY 2007  
IEEE 1394a-2000 CONSUMER ELECTRONICS SOLUTION  
FEATURES  
•
1394 Features  
–
–
SRAM-Like 16-Bit Asynchronous Interface  
(Supports External DMA Only)  
–
–
Integrated 400/200/100 Mbps 2-Port PHY  
PCI Interface (33 MHz) Compliant to PCI  
Specification Version 2.2 (Supports PCI  
Slave and Master Function)  
Compliant to IEEE 1394-1995 and IEEE  
1394a-2000 Standards  
–
–
Supports Bus Manager Functions and  
Automatic 1394 Self-ID Verification  
•
Data Buffers  
–
–
–
3x 4K Byte Isochronous Buffers for Audio  
and Video Data  
Separate Asyncchronous Ack FIFOs  
Decrease the Ack-Tracking Burden on  
External CPU  
2x 2K Byte Asynchronous/Asynchronous  
Stream Transmit Buffers  
•
•
DTLA Encryption Support for MPEG2-DVB,  
DSS, and Audio Data (TSB43DA42 Only)  
2x 2K Byte Asynchronous/Asynchronous  
Stream Receive Buffers  
–
Support for up to Three  
Encrypted/Decrypted Streams at One Time  
–
–
1x 1K Byte Self-ID Buffer  
–
–
Full Ake Performed With Hardware Assist  
Insertion Buffers for MPEG2 Packet  
Insertion (DAT, PMT, SIT, and DIT)  
Secure Method for Loading DTLA  
Information Using Ex-CPU Interface  
–
Programmable Data/Space Available  
Indicators for Buffer Flow Control  
Audio and Video Interfaces  
•
Hardware Packet Formatting for the Following  
Standards  
–
Three Configurable High-Speed Data Ports  
for Video Data  
–
–
–
–
–
IEC61883-1 (General)  
–
Two Ports Configurable as Parallel or  
Serial  
IEC61883-2 (SD-DVCR)  
IEC61883-4 (MPEG2-TS)  
IEC61883-6 (Audio and Music)  
–
One Port Serial Only  
–
Two Interfaces for Audio Data (Only One  
Audio Stream Supported at a Time)  
IEC61883-7 (ITU-R BO.1294 System B) –  
DSS  
–
–
60958 Port  
I2S-Style DAC Interface for PCM Data  
(Two Channel)  
–
–
–
Asynchronous Packets  
Asynchronous Streams  
–
–
Pass-Through Modes for HSDI0 and HSDI1  
PHY Packets (Including Self-IDs)  
Packet Insertion – Two Insertion Buffers  
per HSDI  
•
Additional Features  
–
JTAG Interface to Support Post-Assembly  
Scan of Device I/O – Boundary Scan  
–
PID Filtering (32 PID Filters per HSDI Port)  
•
External CPU Interfaces  
–
Unique Binding Method for Protecting  
Sensitive Off-Chip Data From Ex-CPU  
Interface  
–
Motorola 68K-Style 16-Bit Asynchronous  
Interface (Supports External DMA Only)  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
UNLESS OTHERWISE NOTED this document contains  
PRODUCTION DATA information current as of publication date.  
Products conform to specifications per the terms of Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2007, Texas Instruments Incorporated  
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