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TSB41LV06APZPG4 PDF预览

TSB41LV06APZPG4

更新时间: 2024-01-21 14:06:34
品牌 Logo 应用领域
德州仪器 - TI 驱动接口集成电路驱动器
页数 文件大小 规格书
51页 798K
描述
IEEE 1394a Six-Port Cable Transceiver/Arbiter 100-HTQFP 0 to 70

TSB41LV06APZPG4 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFP包装说明:HTFQFP,
针数:100Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.52差分输出:YES
驱动器位数:12输入特性:DIFFERENTIAL
接口集成电路类型:LINE TRANSCEIVER接口标准:IEEE 1394
JESD-30 代码:S-PQFP-G100JESD-609代码:e4
长度:14 mm湿度敏感等级:3
功能数量:12端子数量:100
最高工作温度:70 °C最低工作温度:
输出特性:DIFFERENTIAL输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:HTFQFP
封装形状:SQUARE封装形式:FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260认证状态:Not Qualified
最大接收延迟:接收器位数:12
座面最大高度:1.2 mm最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
电源电压1-最大:3.6 V电源电压1-分钟:3 V
电源电压1-Nom:3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

TSB41LV06APZPG4 数据手册

 浏览型号TSB41LV06APZPG4的Datasheet PDF文件第2页浏览型号TSB41LV06APZPG4的Datasheet PDF文件第3页浏览型号TSB41LV06APZPG4的Datasheet PDF文件第4页浏览型号TSB41LV06APZPG4的Datasheet PDF文件第5页浏览型号TSB41LV06APZPG4的Datasheet PDF文件第6页浏览型号TSB41LV06APZPG4的Datasheet PDF文件第7页 
ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢈ ꢉ  
ꢊꢋ ꢋꢋ ꢄ ꢌ ꢍ ꢃ ꢎ ꢁꢊ ꢏꢐꢑ ꢒꢓꢀ ꢔꢉꢂ ꢅꢋ ꢀ ꢓꢉꢕꢁ ꢔꢋꢊ ꢆꢋꢓꢖ ꢉ ꢓꢂ ꢊ ꢀꢋ ꢓ  
SLLS363A − SEPTEMBER 1999 − REVISED NOVEMBER 2000  
D
Fully Supports Provisions of IEEE 1394−  
D
Register Bits Give Software Control of  
Contender Bit, Power Class bits, Link  
Active Control Bit and P1394a Features  
1995 Standard for High Performance Serial  
Bus and the P1394a Supplement  
D
D
D
Fully Interoperable With FireWireand  
i.LINKImplementation of IEEE Std 1394  
Fully Compliant With OpenHCI  
Requirements  
D
D
Data Interface to Link-Layer Controller  
Through 2/4/8 Parallel Lines at 49.152 MHz  
Interface to Link Layer Controller Supports  
Low Cost TI Bus-Holder Isolation and  
Optional Annex J Electrical Isolation  
Provides Six P1394a Fully Compliant Cable  
Ports at 100/200/400 Megabits per Second  
(Mbits/s)  
D
D
D
Interoperable With Link-Layer Controllers  
Using 3.3 V and 5 V Supplies  
D
Full P1394a Support Includes: Connection  
Debounce, Arbitrated Short Reset,  
Multispeed Concatenation, Arbitration  
Acceleration, Fly-By Concatenation, Port  
Disable/Suspend/Resume  
Interoperable With Other Physical Layers  
(PHYs) Using 3.3 V and 5 V Supplies  
Low Cost 24.576-MHz Crystal Provides  
Transmit, Receive Data at 100/200/400  
Mbits/s, and Link-Layer Controller Clock at  
49.152 MHz  
D
D
Extended Resume Signaling for  
Compatibility With Legacy DV Devices  
D
D
D
D
D
D
Incoming Data Resynchronized to Local  
Clock  
Power-Down Features to Conserve Energy  
in Battery Powered Applications Include:  
Automatic Device Power-Down During  
Suspend, Device Power-Down Terminal,  
Link Interface Disable via LPS, and Inactive  
Ports Powered-Down  
Logic Performs System Initialization and  
Arbitration Functions  
Encode and Decode Functions Included for  
Data-Strobe Bit Level Encoding  
Separate Cable Bias (TPBIAS) for Each Port  
Single 3.3-V Supply Operation  
D
D
Ultralow-Power Sleep Mode  
Node Power Class Information Signaling  
for System Power Management  
Low Cost High Performance 100-Pin TQFP  
(PZP) Thermally Enhanced Package  
D
Cable Power Presence Monitoring  
D
Direct Drop-In Upgrade for TSB41LV06PZP  
D
Cable Ports Monitor Line Conditions for  
Active Connection to Remote Node  
description  
The TSB41LV06A provides the digital and analog transceiver functions needed to implement a six-port node  
in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The  
transceivers include circuitry to monitor the line conditions as needed for determining connection status, for  
initialization and arbitration, and for packet reception and transmission. The TSB41LV06A is designed to  
interface with a link layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV31,  
TSB12LV41, TSB12LV42, or TSB12LV01A.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.  
i.LINK is a trademark of Sony Corporation  
FireWire is a trademark of Apple Computer, Incorporated.  
ꢀꢣ  
Copyright 2000, Texas Instruments Incorporated  
ꢟ ꢣ ꢠ ꢟꢙ ꢚꢭ ꢜꢛ ꢎ ꢦꢦ ꢤꢎ ꢝ ꢎ ꢞ ꢣ ꢟ ꢣ ꢝ ꢠ ꢨ  
ꢠꢙ  
ꢡꢣ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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型号 品牌 替代类型 描述 数据表
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