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TS87C51RB2-LLAD PDF预览

TS87C51RB2-LLAD

更新时间: 2024-11-23 13:14:55
品牌 Logo 应用领域
爱特美尔 - ATMEL 微控制器
页数 文件大小 规格书
83页 1183K
描述
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TS87C51RB2-LLAD 数据手册

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Features  
80C52 Compatible  
– 8051 pin and instruction compatible  
– Four 8-bit I/O ports  
– Three 16-bit timer/counters  
– 256 bytes scratchpad RAM  
High-Speed Architecture  
– 40 MHz @ 5V, 30MHz @ 3V  
– X2 Speed Improvement capability (6 clocks/machine cycle)  
– 30 MHz @ 5V, 20 MHz @ 3V (Equivalent to  
– 60 MHz @ 5V, 40 MHz @ 3V)  
High  
Dual Data Pointer  
On-chip ROM/EPROM (16K-bytes, 32K-bytes, 64K-bytes)  
On-chip eXpanded RAM (XRAM) (256 or 768 bytes)  
Programmable Clock Out and Up/Down Timer/Counter 2  
Programmable Counter Array with  
– High Speed Output,  
Performance  
8-bit  
Microcontroller  
– Compare / Capture,  
– Pulse Width Modulator,  
– Watchdog Timer Capabilities  
Hardware Watchdog Timer (One-time enabled with Reset-Out)  
2 extra 8-bit I/O ports available on RD2 with high pin count packages  
Asynchronous port reset  
TS80C51RA2  
TS80C51RD2  
TS83C51RB2  
TS83C51RC2  
TS83C51RD2  
TS87C51RB2  
TS87C51RC2  
TS87C51RD2  
Interrupt Structure with  
– 7 Interrupt sources,  
– 4 level priority interrupt system  
Full duplex Enhanced UART  
– Framing error detection  
– Automatic address recognition  
Low EMI (inhibit ALE)  
Power Control modes  
– Idle mode  
– Power-down mode  
– Power-off Flag  
Once mode (On-chip Emulation)  
Power supply: 4.5-5V, 2.7-5.5V  
Temperature ranges: Commercial (0 to 70oC) and Industrial (-40 to 85oC)  
Packages: PDIL40, PLCC44, VQFP44 1.4, PLCC68, VQFP64 1.4  
Description  
Atmel TS8xC51Rx2 is a high performance CMOS ROM, OTP, EPROM and ROMless  
versions of the 80C51 CMOS single chip 8-bit microcontroller.  
The TS8xC51Rx2 retains all features of the 80C51 with extended ROM/EPROM  
capacity (16/32/64 Kbytes), 256 bytes of internal RAM, a 7-source , 4-level interrupt  
system, an on-chip oscilator and three timer/counters.  
In addition, the TS80C51Rx2 has a Programmable Counter Array, an XRAM of 256 or  
768 bytes, a Hardware Watchdog Timer, a more versatile serial channel that facilitates  
multiprocessor communication (EUART) and an X2 speed improvement mechanism.  
The fully static design of the TS80C51Rx2 allows to reduce system power consump-  
tion by bringing the clock frequency down to any value, even DC, without loss of data.  
The TS80C51Rx2 has 2 software-selectable modes of reduced activity for further  
reduction in power consumption. In the idle mode the CPU is frozen while the timers,  
the serial port and the interrupt system are still operating. In the power-down mode the  
RAM is saved and all other functions are inoperative.  
Rev. 4188A–8051–10/02  
1

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