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TS80C52X2-EJBB PDF预览

TS80C52X2-EJBB

更新时间: 2024-11-16 18:53:23
品牌 Logo 应用领域
爱特美尔 - ATMEL 微控制器外围集成电路
页数 文件大小 规格书
56页 689K
描述
Microcontroller, 8-Bit, MROM, CMOS, PQCC44, PLASTIC, LCC-44

TS80C52X2-EJBB 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:LCC
包装说明:QCCJ,针数:44
Reach Compliance Code:compliantHTS代码:8542.31.00.01
风险等级:5.65具有ADC:NO
地址总线宽度:16位大小:8
DAC 通道:NODMA 通道:NO
外部数据总线宽度:8JESD-30 代码:S-PQCC-J44
JESD-609代码:e3长度:16.6 mm
湿度敏感等级:2I/O 线路数量:32
端子数量:44最高工作温度:85 °C
最低工作温度:-40 °CPWM 通道:NO
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):245认证状态:Not Qualified
ROM可编程性:MROM座面最大高度:4.57 mm
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:16.6 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER
Base Number Matches:1

TS80C52X2-EJBB 数据手册

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TS80C52X2  
8-bit CMOS Microcontroller 0-60 MHz  
1. Description  
TEMIC TS80C52X2 is high performance CMOS ROM, The fully static design of the TS80C52X2 allows to  
reduce system power consumption by bringing the clock  
frequency down to any value, even DC, without loss of  
data.  
OTP, EPROM and ROMless versions of the 80C51  
CMOS single chip 8-bit microcontroller.  
The TS80C52X2 retains all features of the TEMIC  
80C51 with extended ROM/EPROM capacity (8  
Kbytes), 256 bytes of internal RAM, a 6-source , 4-level  
interrupt system, an on-chip oscilator and three timer/  
counters.  
The TS80C52X2 has 2 software-selectable modes of  
reduced activity for further reduction in power  
consumption. In the idle mode the CPU is frozen while  
the timers, the serial port and the interrupt system are still  
operating. In the power-down mode the RAM is saved  
and all other functions are inoperative.  
In addition, the TS80C52X2 has a dual data pointer, a  
more versatile serial channel that facilitates  
multiprocessor communication (EUART) and a X2 speed  
improvement mechanism.  
2. Features  
80C52 Compatible  
Interrupt Structure with  
8051 pin and instruction compatible  
Four 8-bit I/O ports  
6 Interrupt sources,  
4 level priority interrupt system  
Three 16-bit timer/counters  
256 bytes scratchpad RAM  
Full duplex Enhanced UART  
Framing error detection  
Automatic address recognition  
High-Speed Architecture  
40 MHz @ 5V, 30MHz @ 3V  
Low EMI (inhibit ALE)  
Power Control modes  
X2 Speed Improvement capability (6 clocks/  
machine cycle)  
Idle mode  
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to  
60 MHz @ 5V, 40 MHz @ 3V)  
Power-down mode  
Power-off Flag  
Dual Data Pointer  
Once mode (On-chip Emulation)  
Power supply: 4.5-5V, 2.7-5.5V  
On-chip ROM/EPROM (8K-bytes)  
Programmable Clock Out and Up/Down Timer/  
Temperature ranges: Commercial (0 to 70oC) and  
Counter 2  
Industrial (-40 to 85oC)  
Asynchronous port reset  
Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP F1  
(13.9 footprint), CQPJ44 (window), CDIL40  
(window)  
Rev. C - Aug. 31, 1999  
1

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