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TS80C51RD2-MJLR PDF预览

TS80C51RD2-MJLR

更新时间： 2024-11-16 17:55:07
品牌 Logo 应用领域
爱特美尔 - ATMEL 时钟微控制器外围集成电路
页数 文件大小 规格书
74页 903K
描述
Microcontroller, 8-Bit, 40MHz, CMOS, PQCC68, PLASTIC, LCC-68

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中文翻译

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TS80C51RD2-MJLR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：LCC
包装说明：QCCJ,针数：68
Reach Compliance Code：compliantECCN代码：3A991.A.2
HTS代码：8542.31.00.01风险等级：5.66
具有ADC：NO地址总线宽度：16
位大小：8最大时钟频率：40 MHz
DAC 通道：NODMA 通道：NO
外部数据总线宽度：8JESD-30 代码：S-PQCC-J68
JESD-609代码：e3长度：24.2316 mm
I/O 线路数量：48端子数量：68
最高工作温度：85 °C最低工作温度：-40 °C
PWM 通道：YES封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：245
认证状态：Not Qualified座面最大高度：4.57 mm
速度：40 MHz最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：24.2316 mmuPs/uCs/外围集成电路类型：MICROCONTROLLER
Base Number Matches：1

TS80C51RD2-MJLR 数据手册

 浏览型号TS80C51RD2-MJLR的Datasheet PDF文件第2页浏览型号TS80C51RD2-MJLR的Datasheet PDF文件第3页浏览型号TS80C51RD2-MJLR的Datasheet PDF文件第4页浏览型号TS80C51RD2-MJLR的Datasheet PDF文件第5页浏览型号TS80C51RD2-MJLR的Datasheet PDF文件第6页浏览型号TS80C51RD2-MJLR的Datasheet PDF文件第7页 
TS80C51RA2/RD2  
TS83C51RB2/RC2/RD2  
TS87C51RB2/RC2/RD2  
High Performance 8-bit Microcontrollers  
1. Description  
Atmel Wireless & Microcontrollers TS80C51Rx2 is high The fully static design of the TS80C51Rx2 allows to  
reduce system power consumption by bringing the clock  
frequency down to any value, even DC, without loss of  
data.  
performance CMOS ROM, OTP, EPROM and ROMless  
versions of the 80C51 CMOS single chip 8-bit  
microcontroller.  
The TS80C51Rx2 has 2 software-selectable modes of  
reduced activity for further reduction in power  
consumption. In the idle mode the CPU is frozen while  
the timers, the serial port and the interrupt system are still  
operating. In the power-down mode the RAM is saved  
and all other functions are inoperative.  
The TS80C51Rx2 retains all features of the 80C51 with  
extended ROM/EPROM capacity (16/32/64 Kbytes), 256  
bytes of internal RAM, a 7-source , 4-level interrupt  
system, an on-chip oscilator and three timer/counters.  
In addition, the TS80C51Rx2 has a Programmable  
Counter Array, an XRAM of 256 or 768 bytes, a  
Hardware Watchdog Timer, a more versatile serial  
channel that facilitates multiprocessor communication  
(EUART) and a X2 speed improvement mechanism.  
2. Features  
•
80C52 Compatible  
•
•
Hardware Watchdog Timer (One-time enabled with  
Reset-Out)  
•
•
•
•
8051 pin and instruction compatible  
Four 8-bit I/O ports  
2 extra 8-bit I/O ports available on RD2 with high  
pin count packages  
Three 16-bit timer/counters  
256 bytes scratchpad RAM  
•
•
Asynchronous port reset  
Interrupt Structure with  
•
High-Speed Architecture  
•
•
7 Interrupt sources,  
•
•
40 MHz @ 5V, 30MHz @ 3V  
4 level priority interrupt system  
X2 Speed Improvement capability (6 clocks/  
machine cycle)  
•
Full duplex Enhanced UART  
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to  
60 MHz @ 5V, 40 MHz @ 3V)  
•
•
Framing error detection  
Automatic address recognition  
•
•
Dual Data Pointer  
•
•
Low EMI (inhibit ALE)  
Power Control modes  
On-chip ROM/EPROM (16K-bytes, 32K-bytes, 64K-  
bytes)  
•
•
•
Idle mode  
•
•
On-chip eXpanded RAM (XRAM) (256 or 768 bytes)  
Power-down mode  
Power-off Flag  
Programmable Clock Out and Up/Down Timer/  
Counter 2  
•
•
•
Once mode (On-chip Emulation)  
•
Programmable Counter Array with  
Power supply: 4.5-5V, 2.7-5.5V  
Temperature ranges: Commercial (0 to 70oC) and  
Industrial (-40 to 85oC)  
•
•
•
•
High Speed Output,  
Compare / Capture,  
Pulse Width Modulator,  
Watchdog Timer Capabilities  
•
Packages: PDIL40, PLCC44, VQFP44 1.4, CQPJ44  
(window), CDIL40 (window), PLCC68, VQFP64  
1.4, JLCC68 (window)  
Rev. C - 06 March, 2001  
1
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