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TS80C31X2-LJBR PDF预览

TS80C31X2-LJBR

更新时间: 2024-11-28 12:58:19
品牌 Logo 应用领域
爱特美尔 - ATMEL 微控制器
页数 文件大小 规格书
42页 368K
描述
Microcontroller, 8-Bit, 30MHz, CMOS, PQCC44, PLASTIC, LCC-44

TS80C31X2-LJBR 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:LCC包装说明:QCCJ,
针数:44Reach Compliance Code:compliant
ECCN代码:3A991.A.2HTS代码:8542.31.00.01
风险等级:5.65Is Samacsys:N
具有ADC:NO地址总线宽度:16
位大小:8最大时钟频率:30 MHz
DAC 通道:NODMA 通道:NO
外部数据总线宽度:8JESD-30 代码:S-PQCC-J44
JESD-609代码:e3长度:16.5862 mm
I/O 线路数量:32端子数量:44
最高工作温度:85 °C最低工作温度:-40 °C
PWM 通道:NO封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:4.57 mm
速度:30 MHz最大供电电压:5.5 V
最小供电电压:2.7 V标称供电电压:3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:16.5862 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER
Base Number Matches:1

TS80C31X2-LJBR 数据手册

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Features  
80C31 Compatible  
8031 pin and instruction compatible  
Four 8-bit I/O ports  
Two 16-bit timer/counters  
128 bytes scratchpad RAM  
High-Speed Architecture  
40 MHz @ 5V, 30MHz @ 3V  
X2 Speed Improvement capability (6 clocks/machine cycle)  
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to 60 MHz @ 5V, 40 MHz @ 3V)  
Dual Data Pointer  
8-bit CMOS  
Microcontroller  
ROMless  
Asynchronous port reset  
Interrupt Structure with  
5 Interrupt sources,  
4 priority level interrupt system  
Full duplex Enhanced UART  
Framing error detection  
TS80C31X2  
AT80C31X2  
Automatic address recognition  
Power Control modes  
Idle mode  
Power-down mode  
Power-off Flag  
Once mode (On-chip Emulation)  
Power supply: 4.5-5.5V, 2.7-5.5V  
Temperature ranges: Commercial (0 to 70oC) and Industrial (-40 to 85oC)  
Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP F1 (13.9 footprint)  
1. Description  
TS80C31X2 is high performance CMOS and ROMless versions of the 80C51 CMOS  
single chip 8-bit microcontroller.  
The TS80C31X2 retains all features of the TSC80C31 with 128 bytes of internal RAM,  
a 5-source, 4 priority level interrupt system, an on-chip oscilator and two  
timer/counters.  
In addition, the TS80C31X2 has a dual data pointer, a more versatile serial channel  
that facilitates multiprocessor communication (EUART) and a X2 speed improvement  
mechanism.  
The fully static design of the TS80C31X2 allows to reduce system power consumption  
by bringing the clock frequency down to any value, even DC, without loss of data.  
The TS80C31X2 has 2 software-selectable modes of reduced activity for further  
reduction in power consumption. In the idle mode the CPU is frozen while the timers,  
the serial port and the interrupt system are still operating. In the power-down mode the  
RAM is saved and all other functions are inoperative.  
4428E–8051–02/08  

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