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TPSM84424MOLR PDF预览

TPSM84424MOLR

更新时间: 2024-02-04 06:25:57
品牌 Logo 应用领域
德州仪器 - TI 开关输出元件电源电路
页数 文件大小 规格书
34页 1309K
描述
采用紧凑型 7.5x7.5mm 封装尺寸的 4.5V 至 17V 输入、0.6V 至 10V 输出、4A 电源模块 | MOL | 24 | -40 to 105

TPSM84424MOLR 技术参数

是否无铅: 不含铅是否Rohs认证: 不符合
生命周期:Active包装说明:,
Reach Compliance Code:compliantECCN代码:EAR99
Factory Lead Time:8 weeks风险等级:1.89
其他特性:OUTPUT VOLTAGE= 0.6V TO 10V模拟集成电路 - 其他类型:SWITCHING REGULATOR
控制技术:PULSE WIDTH MODULATION最大输入电压:17 V
最小输入电压:4.5 V标称输入电压:12 V
JESD-30 代码:S-XQMA-B24长度:7.5 mm
湿度敏感等级:3功能数量:1
端子数量:24最高工作温度:105 °C
最低工作温度:-40 °C最大输出电流:4 A
最大输出电压:10 V最小输出电压:0.6 V
封装主体材料:UNSPECIFIED封装形状:SQUARE
封装形式:MICROELECTRONIC ASSEMBLY峰值回流温度(摄氏度):260
座面最大高度:5.4 mm表面贴装:YES
切换器配置:BUCK最大切换频率:1600 kHz
温度等级:INDUSTRIAL端子形式:BUTT
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

TPSM84424MOLR 数据手册

 浏览型号TPSM84424MOLR的Datasheet PDF文件第3页浏览型号TPSM84424MOLR的Datasheet PDF文件第4页浏览型号TPSM84424MOLR的Datasheet PDF文件第5页浏览型号TPSM84424MOLR的Datasheet PDF文件第7页浏览型号TPSM84424MOLR的Datasheet PDF文件第8页浏览型号TPSM84424MOLR的Datasheet PDF文件第9页 
TPSM84424  
ZHCSHN0A FEBRUARY 2018REVISED APRIL 2018  
www.ti.com.cn  
6.4 Thermal Information  
TPSM84424  
MOL (QFN)  
24 PINS  
22  
THERMAL METRIC(1)  
UNIT  
RθJA  
ψJT  
Junction-to-ambient thermal resistance(2)  
Junction-to-top characterization parameter(3)  
Junction-to-board characterization parameter(4)  
°C/W  
°C/W  
°C/W  
2.1  
ψJB  
13.6  
(1) For more information about thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.  
(2) The junction-to-ambient thermal resistance, RθJA, applies to devices soldered directly to a 100 mm × 100 mm, 4-layer PCB with 2 oz.  
copper and natural convection cooling. Additional airflow reduces RθJA  
.
(3) The junction-to-top board characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a  
procedure described in JESD51-2A (section 6 and 7). TJ = ψJT × Pdis + TT; where Pdis is the power dissipated in the device and TT is  
the temperature of the top of the device.  
(4) The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a  
procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB × Pdis + TB; where Pdis is the power dissipated in the device and TB is  
the temperature of the board 1mm from the device.  
6.5 Electrical Characteristics  
Over –40°C to +105°C ambient temperature, VIN = 12 V, VOUT = 1.2 V, IOUT = IOUTmax, fsw = 450 kHz (unless otherwise  
noted); CIN1 = 2× 10-µF, 25-V, 1210 ceramic; CIN2 = 100-µF, 50-V, electrolytic; COUT = 4× 47-µF, 10-V, 1210 ceramic.  
Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely  
parametric norm and are provided for reference only.  
PARAMETER  
TEST CONDITIONS  
MIN  
4.5(1)  
3.7  
TYP  
MAX UNIT  
INPUT VOLTAGE (VIN  
)
VIN  
Input voltage  
Over IOUT range  
VIN increasing  
VIN decreasing  
VEN = 0 V  
17  
V
V
4.1  
3.9  
3
4.3  
UVLO  
ISHDN  
VIN undervoltage lockout  
Shutdown supply current  
V
11  
10  
µA  
OUTPUT VOLTAGE (VOUT  
)
VOUT(ADJ) Output voltage adjust  
Over IOUT range  
0.6  
V
VOUT(Ripple) Output voltage ripple  
20-MHz bandwidth  
16  
mV  
FEEDBACK  
TA = 25°C, IOUT = 0 A  
0.596  
0.595  
0.6  
0.6  
0.1  
0.8  
0.604  
0.605  
V
V
Feedback voltage(2)  
–40°C TJ 125°C, IOUT = 0 A  
Over VIN range, TA = 25°C, IOUT = 0 A  
Over IOUT range, TA = 25°C  
VFB  
Line regulation  
mV  
mV  
Load regulation  
CURRENT  
Output current  
IOUT  
Natural convection, TA = 25°C  
0
4
A
A
Overcurrent threshold  
11  
PERFORMANCE  
VOUT = 5 V, fSW = 1.2 MHz  
VOUT = 3.3 V, fSW = 1.0 MHz  
94%  
93%  
91%  
87%  
86%  
VIN = 12 V,  
IOUT = 4 A  
ƞ
Efficiency  
VOUT = 1.8 V, fSW = 600 kHz  
VOUT = 1.2 V, fSW = 450 kHz  
VOUT = 1 V, fSW = 400 kHz  
25% to 75% load step, 2A/µs slew rate,  
RTT = 4.02 kΩ,  
COUT = 200-µF ceramic + 220-µF polymer  
27  
35  
mV  
mV  
Transient response  
voltage deviation  
25% to 75% load step, 2A/µs slew rate,  
RTT = 3.40 kΩ, COUT = 200-µF ceramic  
(1) For output voltages 0.6 V to < 5.5 V, the recommended minimum VIN is 4.5 V or (VOUT + 1 V), whichever is greater. For output  
voltages 5.5 V to < 9 V, the recommended minimum VIN is (VOUT + 2 V). For output voltages 9 V to 10 V, the recommended minimum  
VIN is (VOUT + 3 V).  
(2) The overall output voltage tolerance will be affected by the tolerance of the external RFBT and RFBB resistors.  
6
Copyright © 2018, Texas Instruments Incorporated  

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