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TPSM84424MOLR PDF预览

TPSM84424MOLR

更新时间: 2023-09-03 20:37:42
品牌 Logo 应用领域
德州仪器 - TI 开关输出元件电源电路
页数 文件大小 规格书
34页 1309K
描述
采用紧凑型 7.5x7.5mm 封装尺寸的 4.5V 至 17V 输入、0.6V 至 10V 输出、4A 电源模块 | MOL | 24 | -40 to 105

TPSM84424MOLR 技术参数

是否无铅: 不含铅是否Rohs认证: 不符合
生命周期:Active包装说明:,
Reach Compliance Code:compliantECCN代码:EAR99
Factory Lead Time:8 weeks风险等级:1.89
其他特性:OUTPUT VOLTAGE= 0.6V TO 10V模拟集成电路 - 其他类型:SWITCHING REGULATOR
控制技术:PULSE WIDTH MODULATION最大输入电压:17 V
最小输入电压:4.5 V标称输入电压:12 V
JESD-30 代码:S-XQMA-B24长度:7.5 mm
湿度敏感等级:3功能数量:1
端子数量:24最高工作温度:105 °C
最低工作温度:-40 °C最大输出电流:4 A
最大输出电压:10 V最小输出电压:0.6 V
封装主体材料:UNSPECIFIED封装形状:SQUARE
封装形式:MICROELECTRONIC ASSEMBLY峰值回流温度(摄氏度):260
座面最大高度:5.4 mm表面贴装:YES
切换器配置:BUCK最大切换频率:1600 kHz
温度等级:INDUSTRIAL端子形式:BUTT
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

TPSM84424MOLR 数据手册

 浏览型号TPSM84424MOLR的Datasheet PDF文件第1页浏览型号TPSM84424MOLR的Datasheet PDF文件第2页浏览型号TPSM84424MOLR的Datasheet PDF文件第4页浏览型号TPSM84424MOLR的Datasheet PDF文件第5页浏览型号TPSM84424MOLR的Datasheet PDF文件第6页浏览型号TPSM84424MOLR的Datasheet PDF文件第7页 
TPSM84424  
www.ti.com.cn  
ZHCSHN0A FEBRUARY 2018REVISED APRIL 2018  
5 Pin Configuration and Functions  
MOL Package  
24-Pin QFM  
Top View  
24  
23  
22  
21  
1
20  
PGND  
VOUT  
19  
18  
PGND  
PGND  
FB  
AGND  
DNC  
2
3
4
5
6
7
17  
16  
15  
14  
SW  
TT  
SW  
SS/TR  
PGOOD  
PGND  
PGND  
PGND  
8
VOUT  
13  
12  
10  
11  
9
Pin Functions  
PIN  
TYPE(1)  
DESCRIPTION  
NAME  
NO.  
Analog ground. Zero voltage reference for internal references and logic. These pins should be  
connected to one another externally using an analog ground plane on the PCB. Do not connect  
this pin to PGND; the connection is made internal to the device.  
AGND  
3, 9, 23  
G
Do Not Connect. Do not connect this pin to AGND, PGND, or to any other voltage. This pin is  
connected to internal circuitry.  
DNC  
4
Enable. Float or pull high to enable the device. Connect a resistor divider to this pin to implement  
adjustable undervoltage lockout and hysteresis.  
EN  
FB  
10  
2
I
I
Feedback input of the regulator. Connect the output voltage feedback resistor divider to this pin.  
Power ground. This is the return current path for the power stage of the device. Connect these  
pins to the input source, the load, and to the bypass capacitors associated with VIN and VOUT  
using power ground planes on the PCB. Connect pads 12 and 21 to the ground planes using  
multiple vias for improved thermal performance.  
12, 13, 14,  
15, 18, 19,  
20, 21  
PGND  
G
O
Power-good flag. This open drain output asserts low if the output voltage is outside of the PGOOD  
thresholds, VIN is lower than its UVLO threshold, EN is low, device is in thermal shutdown or  
device is in soft-start. Use a 10-kΩ to 100-kΩ pullup resistor to logic rail or other DC voltage no  
higher than 6.5 V.  
PGOOD  
7
Switching frequency setting pin. In RT mode, an external timing resistor adjusts the switching  
frequency. In CLK mode, the device synchronizes to an external clock input to this pin.  
RT/CLK  
SS/TR  
24  
6
I
I
Soft start and tracking pin. Connecting an external capacitor to this pin adjusts the output voltage  
soft-start ramp slower than its 1.25-ms default setting. A voltage applied to this pin allows for  
tracking and sequencing control.  
(1) G = Ground, I = Input, O = Output  
Copyright © 2018, Texas Instruments Incorporated  
3

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