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SGLS325 − JANUARY 2006
D
D
Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D
D
20-Pin TSSOP (PWP) PowerPAD Package
Thermal Shutdown Protection
Enhanced Diminishing Manufacturing
Sources (DMS) Support
PWP PACKAGE
(TOP VIEW)
D
D
D
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D
Enhanced Product-Change Notification
GND/HEATSINK
NC
GND/HEATSINK
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GND
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†
Qualification Pedigree
2-A Low-Dropout (LDO) Voltage Regulator
IN
IN
EN
Open-Drain Power-On Reset With 100-ms
Delay
RESET
FB/SENSE
OUTPUT
OUTPUT
GND/HEATSINK
Ultralow 75-µA Typ Quiescent Current
Fast Transient Response
2% Tolerance Over Specified Conditions
for Fixed-Output Versions
NC
GND/HEATSINK
†
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over the specified
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
NC − No internal connection
description
The TPS75201M-EP is a low dropout regulator with an integrated power-on reset (RESET) function. This device
is capable of supplying 2 A of output current with a dropout of 210 mV. Quiescent current is 75 µA at full load
and drops down to 1 µA when the device is disabled. The TPS75201M-EP is designed to have fast transient
response for larger load current changes.
Because the PMOS device operates like a low-value resistor, the dropout voltage is very low (typically 210 mV
at an output current of 2 A) and is directly proportional to the output current. Additionally, since the PMOS pass
element is a voltage-driven device, the quiescent current is very low and independent of output loading (75 µA
typ over the full range of output current, 1 mA to 2 A). These two key specifications yield a significant
improvement in operating life for battery-powered systems.
The device is enabled when the enable (EN) input is connected to a low-level input voltage. This low-dropout
(LDO) device also features a sleep mode; applying a TTL high signal to EN shuts down the regulator, reducing
the quiescent current to 1 µA at T = 25°C.
J
The RESET (SVS, POR, or power-on reset) output of the TPS75201M-EP initiates a reset in microcomputer
and microprocessor systems in the event of an undervoltage condition. An internal comparator in the
TPS75201M-EP monitors the output voltage of the regulator to detect an undervoltage condition on the
regulated output voltage. When the output reaches 95% of its regulated voltage, RESET goes to a
high-impedance state after a 100-ms delay. RESET goes to a logic-low state when the regulated output voltage
is pulled below 95% (i.e., overload condition) of its regulated voltage.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
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Copyright 2005, Texas Instruments Incorporated
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1
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