TPS715xx
SLVS338P–MAY 2001–REVISED NOVEMBER 2008 .................................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
(2)
PRODUCT
VOUT
TPS715xxyyyz
XX is nominal output voltage (for example, 28 = 2.8 V, 285 = 2.85 V, 01 = Adjustable).
YYY is package designator.
Z is package quantity.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Output voltages from 1.25 V to 5.4 V in 50-mV increments are available through the use of innovative factory EEPROM programming;
minimum order quantities may apply. Contact factory for details and availability.
ABSOLUTE MAXIMUM RATINGS(1)(2)
Over operating temperature range (unless otherwise noted).
UNIT
VIN range
–0.3 V to +24 V
–0.3 V to +16.5 V
Internally limited
2 kV
VOUT range
Peak output current
ESD rating, HBM
ESD rating, CDM
500 V
Continuous total power dissipation
Junction temperature range, TJ
Storage temperature range, Tstg
See Dissipation Rating Table
–40°C to +150°C
–65°C to +150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
DERATING FACTOR
ABOVE TA = +25°C
T
A ≤ 25°C
TA = +70°C
TA = +85°C
BOARD
PACKAGE
RθJC°C/W
RθJA°C/W
POWER RATING POWER RATING POWER RATING
Low-K(1)
High-K(2)
DCK
DCK
165
165
395
315
2.52 mW/°C
3.18 mW/°C
250 mW
320 mW
140 mW
175 mW
100 mW
130 mW
(1) The JEDEC Low-K (1s) board design used to derive this data was a 3 inch × 3 inch, two-layer board with 2 ounce copper traces on top
of the board.
(2) The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch × 3 inch, multilayer board with 1 ounce internal power and
ground planes and 2 ounce copper traces on top and bottom of the board.
2
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