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TPS51916RUK

更新时间： 2024-02-24 17:27:51
品牌 Logo 应用领域
德州仪器 - TI 双倍数据速率
页数 文件大小 规格书
23页 1550K
描述
Using the TPS51916EVM-746 Complete DDR2, DDR3

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TPS51916RUK 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN, LCC20,.11SQ,16针数：20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：0.89
其他特性：OPERATES IN ADJUSTABLE MODE FROM 0.7 TO 1.8V模拟集成电路 - 其他类型：SWITCHING CONTROLLER
控制模式：VOLTAGE-MODE控制技术：PULSE WIDTH MODULATION
最大输入电压：5.5 V最小输入电压：4.5 V
标称输入电压：5 VJESD-30 代码：S-PQCC-N20
JESD-609代码：e4长度：3 mm
湿度敏感等级：2功能数量：1
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C最大输出电压：1.8 V
最小输出电压：0.7 V封装主体材料：PLASTIC/EPOXY
封装代码：HVQCCN封装等效代码：LCC20,.11SQ,16
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：0.75 mm子类别：Switching Regulator or Controllers
标称供电电压 (Vsup)：5 V表面贴装：YES
切换器配置：PUSH-PULL最大切换频率：670 kHz
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：NO LEAD端子节距：0.4 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3 mmBase Number Matches：1

TPS51916RUK 数据手册

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User's Guide  
SLUU526–August 2011  
Using the TPS51916EVM-746 Complete DDR2, DDR3,  
DDR3L, and DDR4 Memory Power Solution Synchronous  
Buck Controller, 2-A LDO, Buffered Reference  
The TPS51916EVM-746 evaluation module (EVM) allows users to evaluate the performance of the  
TPS51916 low-dropout (LDO) regulator. The TPS51916 provides a complete power supply for DDR2,  
DDR3, DDR3L, and DDR4 memory system in the lowest total cost and minimum space. TPS51916  
integrates a synchronous buck controller (VDDQ) with a 2-A sink/source tracking LDO (VTT) and buffered,  
low-noise reference (VTTREF).  
Contents  
1
Description ................................................................................................................... 3  
1.1  
1.2  
Typical Applications ................................................................................................ 3  
Features ............................................................................................................. 3  
2
3
4
Electrical Performance Specifications .................................................................................... 3  
Schematic .................................................................................................................... 5  
Test Setup ................................................................................................................... 6  
4.1  
4.2  
Test Equipment ..................................................................................................... 6  
Recommended Test Setup ....................................................................................... 7  
5
6
Configurations ............................................................................................................... 8  
5.1  
S3, S5 Enable Selection .......................................................................................... 8  
Test Procedure .............................................................................................................. 8  
6.1  
6.2  
6.3  
Line/Load Regulation and Efficiency Measurement Procedure .............................................. 8  
List of Test Points .................................................................................................. 8  
Equipment Shutdown .............................................................................................. 9  
7
Performance Data and Typical Characteristic Curves ................................................................. 9  
7.1  
7.2  
7.3  
7.4  
7.5  
7.6  
7.7  
7.8  
7.9  
DDR3 VDDQ Efficiency ........................................................................................... 9  
DDR3 VDDQ Load Regulation .................................................................................. 10  
DDR3 VDDQ Line Regulation .................................................................................. 10  
DDR3 VTT Load Regulation .................................................................................... 11  
DDR3 VTTREF Load Regulation ............................................................................... 11  
DDR3 VTT Dropout Voltage .................................................................................... 12  
DDR3 S5 Enable Turnon/Turnoff ............................................................................... 12  
S5 Enable Turnon with 1-V Prebias at VDDQ ................................................................ 13  
DDR3 S3 Enable Turnon/ Turnoff (S5 is ON) ................................................................ 13  
7.10 DDR3 VDDQ Output Ripple ..................................................................................... 14  
7.11 DDR3 VDDQ Switching Node .................................................................................. 14  
7.12 DDR3 VDDQ Output Transient ................................................................................. 15  
7.13 DDR3 VTT Transient With 1.5-A Sinking and Sourcing Current ........................................... 15  
7.14 Thermal Image .................................................................................................... 16  
7.15 DDR3 VDDQ Bode Plot ......................................................................................... 16  
7.16 DDR3 VTT Bode Plot ............................................................................................ 17  
EVM Assembly Drawing and PCB Layout ............................................................................. 17  
Bill of Materials ............................................................................................................. 21  
8
9
List of Figures  
D-CAP2 is a trademark of Texas Instruments.  
1
SLUU526–August 2011  
Submit Documentation Feedback  
Using the TPS51916EVM-746 Complete DDR2, DDR3, DDR3L, and DDR4  
Memory Power Solution Synchronous Buck Controller, 2-A LDO, Buffered  
Copyright © 2011, Texas Instruments Incorporated  
Reference  
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