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TPL7407LAQPWRQ1 PDF预览

TPL7407LAQPWRQ1

更新时间： 2024-01-07 14:50:57
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管接口集成电路驱动器
页数 文件大小 规格书
22页 838K
描述
30V、7 通道汽车类 NMOS 阵列低侧驱动器 | PW | 16 | -40 to 125

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TPL7407LAQPWRQ1 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：TSSOP,
Reach Compliance Code：compliantECCN代码：EAR99
风险等级：1.69内置保护：TRANSIENT
驱动器位数：7接口集成电路类型：BUFFER OR INVERTER BASED PERIPHERAL DRIVER
JESD-30 代码：R-PDSO-G16长度：5 mm
湿度敏感等级：2功能数量：7
端子数量：16最高工作温度：125 °C
最低工作温度：-40 °C输出电流流向：SINK
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260筛选级别：AEC-Q100
座面最大高度：1.2 mm表面贴装：YES
温度等级：AUTOMOTIVE端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.4 mm
Base Number Matches：1

TPL7407LAQPWRQ1 数据手册

 浏览型号TPL7407LAQPWRQ1的Datasheet PDF文件第4页浏览型号TPL7407LAQPWRQ1的Datasheet PDF文件第5页浏览型号TPL7407LAQPWRQ1的Datasheet PDF文件第6页浏览型号TPL7407LAQPWRQ1的Datasheet PDF文件第8页浏览型号TPL7407LAQPWRQ1的Datasheet PDF文件第9页浏览型号TPL7407LAQPWRQ1的Datasheet PDF文件第10页 
TPL7407LA-Q1  
www.ti.com.cn  
ZHCSIA6 –MAY 2018  
7 Detailed Description  
7.1 Overview  
The TPL740LA-Q1 integrates seven low side NMOS transistors that are capable of sinking up to 600 mA and  
wide GPIO range capability.  
The TPL7407LA-Q1 comprises seven high voltage, high current NMOS transistors tied to a common ground  
driven by internal level shifting and gate drive circuitry. The TPL7407LA-Q1 offers solutions to many interface  
needs, including solenoids, relays, lamps, small motors, and LEDs. Applications requiring sink currents beyond  
the capability of a single output may be accommodated by paralleling the outputs.  
The TPL7407LA-Q1 also enables pin to pin replacement with legacy 7 channel darlington pair implementations.  
This device can operate over a wide temperature range (–40°C to +125°C).  
7.2 Functional Block Diagram  
COM  
Regulation  
Circuitry  
OUT(1-7)  
50 k  
IN(1-7)  
DRIVER  
OVP  
1M  
7.3 Feature Description  
Each channel of the TPL7407LA-Q1 consists of high power low side NMOS transistors driven by level shifting  
and gate driving circuitry. The gate drivers allow for high output current drive with a very low input voltage,  
meaning full operation with low GPIO voltages.  
In order to enable floating inputs a 1-MΩ pull-down resistor exists on each channel. Another 50-kΩ resistor exists  
between the input and gate driving circuitry. This exists to limit the input current whenever there is an over  
voltage and the internal Zener clamps. It also interacts with the inherent capacitance of the gate driving circuitry  
to behave as an RC snubber to help prevent spurious switching in noisy environment.  
In order to power the gate driving circuitry an LDO exists. See the Power Supply Recommendations section for  
further detail on this circuitry.  
The diodes connected between the output and COM pin is used to suppress kick-back voltage from an inductive  
load that is excited when the NMOS drivers are turned off (stop sinking) and the stored energy in the coils  
causes a reverse current to flow into the coil supply.  
7.4 Device Functional Modes  
7.4.1 Inductive Load Drive  
When the COM pin is tied to the coil supply voltage, the TPL7407LA-Q1 is able to drive inductive loads and  
suppress the kick-back voltage via the internal free wheeling diodes.  
7.4.2 Resistive Load Drive  
When driving a resistive load, a pull-up resistor is needed in order for the TPL7407LA-Q1 to sink current and for  
there to be a logic high level. The COM pin must be supplied ≥ 6.5 V for full functionality.  
版权 © 2018, Texas Instruments Incorporated  
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