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TP2540N3 PDF预览

TP2540N3

更新时间： 2024-11-22 22:36:35
品牌 Logo 应用领域
超科 - SUPERTEX /
页数 文件大小 规格书
4页 481K
描述
P-Channel Enhancement-Mode Vertical DMOS FETs

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中文翻译

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TP2540N3 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete包装说明：CYLINDRICAL, O-PBCY-W3
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8541.21.00.95风险等级：5.24
其他特性：LOGIC LEVEL COMPATIBLE, HIGH INPUT IMPEDANCE配置：SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压：400 V最大漏极电流 (ID)：0.086 A
最大漏源导通电阻：30 ΩFET 技术：METAL-OXIDE SEMICONDUCTOR
最大反馈电容 (Crss)：25 pFJEDEC-95代码：TO-92
JESD-30 代码：O-PBCY-W3JESD-609代码：e0
元件数量：1端子数量：3
工作模式：ENHANCEMENT MODE最高工作温度：150 °C
封装主体材料：PLASTIC/EPOXY封装形状：ROUND
封装形式：CYLINDRICAL峰值回流温度（摄氏度）：NOT SPECIFIED
极性/信道类型：P-CHANNEL功耗环境最大值：1 W
最大功率耗散 (Abs)：1 W认证状态：Not Qualified
子类别：Other Transistors表面贴装：NO
端子面层：Tin/Lead (Sn/Pb)端子形式：WIRE
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
晶体管应用：SWITCHING晶体管元件材料：SILICON
Base Number Matches：1

TP2540N3 数据手册

 浏览型号TP2540N3的Datasheet PDF文件第2页浏览型号TP2540N3的Datasheet PDF文件第3页浏览型号TP2540N3的Datasheet PDF文件第4页 
TP2535  
TP2540  
Low Threshold  
P-Channel Enhancement-Mode  
Vertical DMOS FETs  
Ordering Information  
Order Number / Package  
BVDSS  
/
RDS(ON)  
VGS(th)  
ID(ON)  
(min)  
BVDGS  
-350V  
-400V  
(max)  
(max)  
TO-92  
TO-243AA*  
—
Die†  
—
25Ω  
25Ω  
-2.4V  
-2.4V  
-0.4A  
-0.4A  
TP2535N3  
TP2540N3  
TP2540N8  
TP2540ND  
* Same as SOT-89. Product supplied on 2000 piece carrier tape reels.  
†
MIL visual screening available.  
Product marking for TO-243AA  
Features  
TP5D❋  
Where ❋ = 2-week alpha date code  
❏
❏
❏
❏
❏
❏
❏
❏
Low threshold — -2.4V max.  
High input impedance  
Low input capacitance — 125pF max.  
Fast switching speeds  
Low Threshold DMOS Technology  
Low on resistance  
These low threshold enhancement-mode (normally-off) transis-  
tors utilize a vertical DMOS structure and Supertex's well-proven  
silicon-gate manufacturing process. This combination produces  
devices with the power handling capabilities of bipolar transistors  
and with the high input impedance and positive temperature  
coefficient inherent in MOS devices. Characteristic of all MOS  
structures, these devices are free from thermal runaway and  
thermally-induced secondary breakdown.  
Free from secondary breakdown  
Low input and output leakage  
Complementary N- and P-channel devices  
Applications  
Supertex’s vertical DMOS FETs are ideally suited to a wide range  
of switching and amplifying applications where very low threshold  
voltage, highbreakdownvoltage, highinputimpedance, lowinput  
capacitance, and fast switching speeds are desired.  
❏
❏
❏
❏
❏
❏
❏
Logic level interfaces – ideal for TTL and CMOS  
Solid state relays  
Battery operated systems  
Photo voltaic drives  
Analog switches  
Package Options  
General purpose line drivers  
Telecom switches  
Absolute Maximum Ratings  
D
Drain-to-Source Voltage  
Drain-to-Gate Voltage  
Gate-to-Source Voltage  
BVDSS  
BVDGS  
± 20V  
G
D
S
S G  
D
TO-243AA  
(SOT-89)  
TO-92  
Operating and Storage Temperature  
-55°C to +150°C  
300°C  
Soldering Temperature*  
* Distance of 1.6 mm from case for 10 seconds.  
Note: See Package Outline section for dimensions.  
11/12/01  
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability  
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to  
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the  
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.  
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