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TP2424 PDF预览

TP2424

更新时间: 2023-12-06 20:08:57
品牌 Logo 应用领域
美国微芯 - MICROCHIP /
页数 文件大小 规格书
12页 264K
描述
This low threshold enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure a

TP2424 数据手册

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TP2424  
P-Channel Enhancement-Mode Vertical DMOS FET  
Features  
General Description  
• Low Threshold  
The TP2424 low-threshold Enhancement-mode  
(normally-off) transistor uses a vertical DMOS structure  
and a well-proven silicon-gate manufacturing process.  
This combination produces a device with the power  
handling capabilities of bipolar transistors and the high  
input impedance and positive temperature coefficient  
inherent in MOS devices. Characteristic of all MOS  
structures, this device is free from thermal runaway and  
thermally induced secondary breakdown.  
• High Input Impedance  
• Low Input Capacitance  
• Fast Switching Speeds  
• Free from Secondary Breakdown  
• Low Input and Output Leakage  
Applications  
Microchip’s vertical DMOS FETs are ideally suited to a  
wide range of switching and amplifying applications  
where very low threshold voltage, high breakdown  
voltage, high input impedance, low input capacitance  
and fast switching speeds are desired.  
• Logic-Level Interfaces (Ideal for TTL and CMOS)  
• Solid-State Relays  
• Linear Amplifiers  
• Analog Switches  
• Power Management  
Telecommunication Switches  
Package Type  
3-lead SOT-89  
(Top view)  
DRAIN  
SOURCE  
DRAIN  
GATE  
See Table 2-1 for pin information.  
2019 Microchip Technology Inc.  
DS20005959A-page 1  

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