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TMS320F2812ZHH

更新时间： 2024-11-19 02:44:03
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德州仪器 - TI /
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173页 2472K
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TMS320F281x Digital Signal Processors

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TMS320F2810, TMS320F2811, TMS320F2812  
SPRS174U –APRIL 2001–REVISED JULY 2019  
TMS320F281x Digital Signal Processors  
1 Device Overview  
1.1 Features  
1
• High-performance static CMOS technology  
– 150 MHz (6.67-ns cycle time)  
• Clock and system control  
– On-chip oscillator  
– Low-power (1.8-V core at 135 MHz,  
1.9-V core at 150 MHz, 3.3-V I/O) design  
– Watchdog timer module  
• Three external interrupts  
• JTAG boundary scan support  
• Peripheral Interrupt Expansion (PIE) block that  
supports 45 peripheral interrupts  
• Three 32-bit CPU timers  
– IEEE Standard 1149.1-1990 IEEE Standard  
Test Access Port and Boundary-Scan  
Architecture  
• 128-bit security key/lock  
• High-performance 32-bit CPU (TMS320C28x)  
– 16 × 16 and 32 × 32 MAC operations  
– 16 × 16 dual MAC  
– Protects flash/OTP and L0/L1 SARAM  
– Prevents firmware reverse-engineering  
• Motor control peripherals  
– Two Event Managers (EVA, EVB)  
– Compatible to 240xA devices  
• Serial port peripherals  
– Harvard bus architecture  
– Atomic operations  
– Fast interrupt response and processing  
– Unified memory programming model  
– 4M linear program/data address reach  
– Code-efficient (in C/C++ and Assembly)  
– Serial Peripheral Interface (SPI)  
– Two Serial Communications Interfaces (SCIs),  
standard UART  
– TMS320F24x/LF240x processor source code  
compatible  
• On-chip memory  
– Enhanced Controller Area Network (eCAN)  
– Multichannel Buffered Serial Port (McBSP)  
• 12-bit ADC, 16 channels  
– Up to 128K × 16 flash  
(Four 8K × 16 and six 16K × 16 sectors)  
– 1K × 16 OTP ROM  
– L0 and L1: 2 blocks of 4K × 16 each Single-  
Access RAM (SARAM)  
– 2 × 8 channel input multiplexer  
– Two Sample-and-Hold  
– Single/simultaneous conversions  
– Fast conversion rate: 80 ns/12.5 MSPS  
• Up to 56 General-Purpose I/O (GPIO) pins  
• Advanced emulation features  
– Analysis and breakpoint functions  
– Real-time debug via hardware  
• Development tools include  
– H0: 1 block of 8K × 16 SARAM  
– M0 and M1: 2 blocks of 1K × 16 each SARAM  
• Boot ROM (4K × 16)  
– With software boot modes  
– Standard math tables  
• External interface (F2812)  
– Over 1M × 16 total memory  
– Programmable wait states  
– Programmable read/write strobe timing  
– Three individual chip selects  
• Endianness: Little endian  
– ANSI C/C++ compiler/assembler/linker  
– Code Composer Studio™ IDE  
– DSP/BIOS™  
– JTAG scan controllers  
– IEEE Standard 1149.1-1990 IEEE Standard  
Test Access Port and Boundary-Scan  
Architecture  
• Low-power modes and power savings  
– IDLE, STANDBY, HALT modes supported  
– Disable individual peripheral clocks  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 
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