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TMS320C6211GFN-167 PDF预览

TMS320C6211GFN-167

更新时间: 2024-11-21 19:42:27
品牌 Logo 应用领域
德州仪器 - TI 时钟外围集成电路
页数 文件大小 规格书
89页 1245K
描述
32-BIT, 166.67MHz, OTHER DSP, PBGA256, 27 X 27 MM, PLASTIC, BGA-256

TMS320C6211GFN-167 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:27 X 27 MM, PLASTIC, BGA-256针数:256
Reach Compliance Code:unknown风险等级:5.82
其他特性:ALSO REQUIRES 3.3V SUPPLY地址总线宽度:22
桶式移位器:NO边界扫描:YES
最大时钟频率:166.67 MHz外部数据总线宽度:32
格式:FIXED POINT内部总线架构:MULTIPLE
JESD-30 代码:S-PBGA-B256长度:27 mm
低功率模式:YES端子数量:256
最高工作温度:90 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装形状:SQUARE封装形式:GRID ARRAY
认证状态:Not Qualified座面最大高度:2.32 mm
最大供电电压:1.89 V最小供电电压:1.71 V
标称供电电压:1.8 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM宽度:27 mm
uPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches:1

TMS320C6211GFN-167 数据手册

 浏览型号TMS320C6211GFN-167的Datasheet PDF文件第2页浏览型号TMS320C6211GFN-167的Datasheet PDF文件第3页浏览型号TMS320C6211GFN-167的Datasheet PDF文件第4页浏览型号TMS320C6211GFN-167的Datasheet PDF文件第5页浏览型号TMS320C6211GFN-167的Datasheet PDF文件第6页浏览型号TMS320C6211GFN-167的Datasheet PDF文件第7页 
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢄ ꢈꢈ ꢉ ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢄ ꢈꢈꢊ  
ꢋ ꢌꢍ ꢎꢏꢐꢑꢒ ꢌ ꢓꢀ ꢏꢌ ꢔꢌ ꢀꢕꢖ ꢂꢌ ꢔ ꢓꢕꢖ ꢑꢗ ꢒ ꢆꢎ ꢂ ꢂꢒ ꢗ ꢂ  
SPRS073L − AUGUST 1998 − REVISED JUNE 2005  
D
D
Excellent Price/Performance Digital Signal  
Processors (DSPs): TMS320C62x  
(TMS320C6211 and TMS320C6211B)  
− Eight 32-Bit Instructions/Cycle  
− C6211, C6211B, C6711, and C6711B are  
Pin-Compatible  
− 150-, 167-MHz Clock Rates  
− 6.7-, 6-ns Instruction Cycle Time  
1200, 1333 MIPS  
D
Device Configuration  
− Boot Mode: HPI, 8-, 16-, and 32-Bit ROM  
Boot  
− Endianness: Little Endian, Big Endian  
D
32-Bit External Memory Interface (EMIF)  
− Glueless Interface to Asynchronous  
Memories: SRAM and EPROM  
− Glueless Interface to Synchronous  
Memories: SDRAM and SBSRAM  
− 512M-Byte Total Addressable External  
Memory Space  
− Extended Temperature Device (C6211B)  
VelociTIAdvanced Very Long Instruction  
Word (VLIW) C62xDSP Core (C6211/11B)  
− Eight Highly Independent Functional  
Units:  
D
D
D
Enhanced Direct-Memory-Access (EDMA)  
Controller (16 Independent Channels)  
16-Bit Host-Port Interface (HPI)  
− Access to Entire Memory Map  
− Six ALUs (32-/40-Bit)  
− Two 16-Bit Multipliers (32-Bit Results)  
− Load-Store Architecture With 32 32-Bit  
General-Purpose Registers  
− Instruction Packing Reduces Code Size  
− All Instructions Conditional  
Two Multichannel Buffered Serial Ports  
(McBSPs)  
− Direct Interface to T1/E1, MVIP, SCSA  
Framers  
− ST-Bus-Switching Compatible  
− Up to 256 Channels Each  
− AC97-Compatible  
− Serial-Peripheral-Interface (SPI)  
Compatible (Motorola)  
D
D
Instruction Set Features  
− Byte-Addressable (8-, 16-, 32-Bit Data)  
− 8-Bit Overflow Protection  
− Saturation  
− Bit-Field Extract, Set, Clear  
− Bit-Counting  
D
D
Two 32-Bit General-Purpose Timers  
− Normalization  
Flexible Phase-Locked-Loop (PLL) Clock  
Generator  
L1/L2 Memory Architecture  
− 32K-Bit (4K-Byte) L1P Program Cache  
(Direct Mapped)  
− 32K-Bit (4K-Byte) L1D Data Cache  
(2-Way Set-Associative)  
D
D
D
D
IEEE-1149.1 (JTAG )  
Boundary-Scan-Compatible  
256-Pin Ball Grid Array (BGA) Package  
(GFN and ZFN Suffixes)  
− 512K-Bit (64K-Byte) L2 Unified Mapped  
RAM/Cache  
0.18-µm/5-Level Metal Process  
− CMOS Technology  
(Flexible Data/Program Allocation)  
3.3-V I/Os, 1.8-V Internal  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
TMS320C62x, VelociTI, and C62x are trademarks of Texas Instruments.  
Motorola is a trademark of Motorola, Inc.  
All trademarks are the property of their respective owners.  
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
ꢀꢤ  
Copyright 2004, Texas Instruments Incorporated  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
1
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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