TLV5535
8-BIT, 35 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER
SLAS221 – JUNE 1999
recommended operating conditions over operating free-temperature range
power supply
MIN NOM
MAX
UNIT
AV
DD
– AV
SS
Supply voltage
DV
– DV
3
3.3
3.6
V
DD
DRV
SS
– DRV
DD
SS
analog and reference inputs
MIN
NOM
MAX
UNIT
Reference input voltage (top), V
(REFTI)
(NOM) – 0.2 2 + (AV
– 3)
(NOM) + 0.2
1.2
V
V
V
V
DD
Reference input voltage (bottom), V
(REFBI)
0.8
1
Reference voltage differential, V
(REFTI)
– V
1 + (AV – 3)
DD
(REFBI)
Analog input voltage, V
V
V
(REFTI)
(AIN)
(REFBI)
digital inputs
MIN NOM
MAX
UNIT
V
High-level input voltage, V
IH
2.0
DV
DD
0.2xDV
Low-level input voltage, V
DGND
V
IL
DD
Clock period, t
28.6
13
ns
ns
c
Pulse duration, clock high, t
w(CLKH)
Pulse duration, clock low, t
w(CLKL)
13
ns
electrical characteristics over recommended operating conditions, f
voltage references (unless otherwise noted)
= 35 MSPS, external
CLK
power supply
PARAMETER
TEST CONDITIONS
MIN
TYP
27
MAX
34
UNIT
AV
DD
AV
= DV
= 3.3 V, DRV
= 15 pF, V = 1 MHz, –1-dB FS
= 3 V,
DD
DD
DD
I
Operating supply current
DV
1.5
4
2.6
6
mA
DD
DD
DRV
C
L
I
DD
PWDN_REF = L
106
90
139
113
15
P
P
Power dissipation
Standby power
D
PWDN_REF = H
mW
STBY = H, CLK held high or low
11
D(STBY)
digital logic inputs
PARAMETER
High-level input current on CLK
TEST CONDITIONS
MIN
TYP
MAX
UNIT
†
I
I
AV
AV
= DV
= DV
= DRV
= DRV
= CLK = 3.6 V
= 3.6 V,
10
µA
IH
DD
DD
DD
DD
Low-level input current on digital inputs
(OE, STDBY, PWDN_REF, CLK)
DD
DD
10
µA
IL
Digital inputs at 0 V
C
Input capacitance
5
pF
I
†
I
leakage current on other digital inputs (OE, STDBY, PWDN_REF) is not measured since these inputs have an internal pull-down resistor of
IH
4 KΩ to DGND.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265