TLV5535
8-BIT, 35 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER
SLAS221 – JUNE 1999
electrical characteristics over recommended operating conditions, f
voltage references (unless otherwise noted) (continued)
= 35 MSPS, external
CLK
logic outputs
PARAMETER
TEST CONDITIONS
= DRV = 3 V at I
MIN
TYP
MAX
UNIT
AV
DD
= DV
= 50 µA,
OH
DD
DD
V
V
High-level output voltage
2.8
V
OH
Digital output forced high
AV = DV = DRV
Digital output forced low
= 3.6 V at I
= 50 µA,
OL
DD DD
DD
Low-level output voltage
Output capacitance
0.1
V
OL
C
5
pF
µA
O
High-impedance state output current to
high level
I
10
10
OZH
AV
DD
= DV
= DRV = 3.6 V
DD
DD
High-impedance state output current to
low level
I
µA
OZL
dc accuracy
PARAMETER
TEST CONDITIONS
MIN
–1.5
–2.4
–1
TYP
±0.7
±0.7
±0.6
MAX
1.5
2.4
1.3
5
UNIT
LSB
LSB
LSB
%FS
%FS
T
= 25°C
A
Integral nonlinearity (INL), best-fit
Internal references (see Note 1)
Internal references (see Note 2),
T
= –40°C to 85°C
T = –40°C to 85°C
A
A
Differential nonlinearity (DNL)
Zero error
AV
DD
= DV
= 3.3 V, DRV = 3 V,
DD DD
Internal references (see Note 3)
Full-scale error
5
NOTES: 1. Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The point used as zero
occurs 1/2 LSB before the first code transition. The full-scale point is defined as a level 1/2 LSB beyond the last code transition. The
deviation is measured from the center of each particular code to the true straight line between these two endpoints.
2. AnidealADCexhibitscodetransitionsthatareexactly1LSBapart. DNListhedeviationfromthisidealvalue.Thereforethismeasure
indicates how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under
n
test [i.e., (last transition level – first transition level) ÷ (2 – 2)]. Using this definition for DNL separates the effects of gain and offset
error. A minimum DNL better than –1 LSB ensures no missing codes.
3. Zero error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that switches
the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the
bottom reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by
the number of ADC output levels (256).
Full-scale error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that switches
the ADC output from code 254 to code 255. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5
LSB from the top reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references
divided by the number of ADC output levels (256).
analog input
PARAMETER
Input capacitance
TEST CONDITIONS
MIN
TYP
MAX
UNIT
C
4
pF
I
5
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