Datasheet > TLV5535IPW

TLV5535IPW

更新时间： 2024-01-05 09:06:57

品牌	Logo	应用领域
德州仪器 - TI		转换器
页数	文件大小	规格书
32页	535K
描述
8-BIT, 35 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER

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技术参数
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TLV5535IPW 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.84
Base Number Matches：	1

TLV5535IPW 数据手册

TLV5535

8-BIT, 35 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER

SLAS221 – JUNE 1999

electrical characteristics over recommended operating conditions, f

voltage references (unless otherwise noted) (continued)

= 35 MSPS, external

CLK

timing requirements

PARAMETER

Maximum conversion rate

Minimum conversion rate

Output delay time (see Figure 1)

Output hold time

TEST CONDITIONS

MIN

TYP

MAX

UNIT

MHz

kHz

CLK

= 10 pF,

= 2 pF,

See Notes 5 and 6

See Note 5

d(o)

h(o)

CLK

cycles

Pipeline delay time (latency)

See Note 6

4.5

d(pipe)

Aperture delay time

1.5

ps, rms

d(a)

j(a)

dis

Aperture jitter

See Note 5

Disable time, OE rising to Hi-Z

Enable time, OE falling to valid data

NOTES: 5. Outputtiming t

d(o)

is measured from the 1.5 V level oftheCLKinputfallingedgetothe10%/90%levelofthedigitaloutput. Thedigital

output load is not higher than 10 pF.

Output hold time t is measured from the 1.5 V level of the CLK input falling edge to the 10%/90% level of the digital output. The

h(o)

digital output is load is not less than 2 pF.

Aperture delay t is measured from the 1.5 V level of the CLK input to the actual sampling instant.

d(A)

The OE signal is asynchronous.

OE timing t is measured from the V

level of OE to the high-impedance state of the output data. The digital output load is

dis IH(MIN)

not higher than 10 pF.

OE timing t is measured from the V

levels. The digital output load is not higher than 10 pF.

level of OE to the instant when the output data reaches V

OH(min)

or V

output

OL(max)

en IL(MAX)

6. The number of clock cycles between conversion initiation on an input sample and the corresponding output data being made

available from the ADC pipeline. Once the data pipeline is full, new valid output data is provided on every clock cycle. In order to

know when data is stable on the output pins, the output delay time t

(i.e., the delay time through the digital output buffers) needs

is more than 1/2 clock period at 35 MHz, data cannot be reliably

d(o)

to be added to the pipeline latency. Note that since the max t

d(o)

clocked in on a rising edge of CLK at this speed. The falling edge should be used.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1...4 5 678 9 10...32

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