TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
D OR PW PACKAGE
(TOP VIEW)
Conversion Time ≤ 10 µs
10-Bit-Resolution ADC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Programmable Power-Down
Mode . . . 1 µA
DATA OUT
DATA IN
I/O CLK
EOC
CS
REF+
REF–
FS
INV CLK
GND
CSTART
A3
Wide Range Single-Supply Operation of
2.7 V dc to 5.5 V dc
V
CC
A0
Analog Input Range of 0 V to V
CC
Built-in Analog Multiplexer with 8 Analog
Input Channels
A1
A2
TMS320 DSP and Microprocessor SPI and
QSPI Compatible Serial Interfaces
DB OR J PACKAGE
(TOP VIEW)
End-of-Conversion (EOC) Flag
Inherent Sample-and-Hold Function
Built-In Self-Test Modes
1
2
3
4
5
6
7
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9
10
20
19
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12
11
A0
A1
A2
A3
A4
A5
A6
A7
V
CC
EOC
I/O CLK
DATA IN
DATA OUT
CS
REF+
REF–
FS
INV CLK
Programmable Power and Conversion Rate
Asynchronous Start of Conversion for
Extended Sampling
Hardware I/O Clock Phase Adjust Input
CSTART
GND
description
The TLV1544 and TLV1548 are CMOS 10-bit
switched-capacitor successive-approximation (SAR)
analog-to-digital (A/D) converters. Each device
has a chip select (CS), input-output clock (I/O
CLK), data input (DATA IN) and serial data output
(DATA OUT) that provide a direct 4-wire
synchronous serial peripheral interface (SPI ,
QSPI ) port of a host microprocessor. When
interfacing with a TMS320 DSP, an additional
frame sync signal (FS) indicates the start of a
serial data frame. The devices allow high-speed
data transfers from the host. The INV CLK input
provides further timing flexibility for the serial
interface.
FK PACKAGE
(TOP VIEW)
3
2
1
20 19
A3
I/O CLK
18
4
5
6
7
8
A4
A5
A6
A7
DATA IN
DATA OUT
CS
17
16
15
14
REF+
9
10 11 12 13
In addition to a high-speed converter andversatile
control capability, the device has an on-chip
11-channel multiplexer that can select any one of
eight analog inputs or any one of three internal self-test voltages. The sample-and-hold function is automatic
except for the extended sampling cycle, where the sampling cycle is started by the falling edge of asynchronous
CSTART. At the end of the A/D conversion, the end-of-conversion (EOC) output goes high to indicate that the
conversion is complete. The TLV1544 and TLV1548 are designed to operate with a wide range of supply
voltages with very low power consumption. The power saving feature is further enhanced with a
software-programmed power-down mode and conversion rate. The converter incorporated in the device
features differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and
isolation of analog circuitry from logic and supply noise. A switched-capacitor design allows low-error
conversion over the full operating temperature range.
SPI and QSPI are registered trademarks of Motorola, Inc.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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